Design of multi-channel ADC system based on DSP and CPLD technology

Introduction
--- With the application and development of modern electronic technology, the content of digital signal processing is becoming increasingly complex, and ADC is an inevitable process to achieve conversion from analog to digital. In response to this situation, a multi-channel ADC system design method is proposed using digital signal processors and programmable logic devices, which realizes the sampling, transmission and processing of dynamic multi-channel analog input signals, simplifying circuit design, and programmable logic devices enable The system's versatility and portability are well extended. The system block diagram is shown in Figure 1.

System Hardware Design
　　The ADC device used in this design is the low-power 16-bit analog-to-digital converter (ADC) MAX1162 produced by MAXIM Company. MAX1162 adopts a successive approximation ADC structure, with automatic shutdown, 1.1μs fast wake-up and high-speed interface compatible with SPI/QSPI/MICROWIRE. It uses a +5V single analog power supply and has an independent digital power pin, allowing the chip to directly connect to + 2.7~+5.25V digital logic interface. The REF pin is connected to an external reference voltage, used to set the analog input voltage range, and is connected to a 4.7μF electrolytic capacitor to the analog ground; the AVDD pin is a +5V power supply input terminal, and is connected to a 0.1μF capacitor to the analog ground. Capacitor; AGND is analog ground; CS is chip select input, active low. When it is high, the system is in power-down mode. When it changes from high to low, it activates the system to normal operating mode and initializes a conversion. This system chooses as the enable signal of AD; SCLK is the serial clock input, driving the analog-to-digital conversion process; DOUT is the serial data output, and the data status changes on the falling edge of SCLK; DGND is the digital ground; DVDD is the digital voltage supply, Connect a 0.1μF capacitor to the digital ground; AIN is the analog signal input terminal.

　　The central control unit of the ADC system uses TI (Texas Instruments) floating-point digital signal processor TMS320VC33-150. The address bus of TMS320VC33 is 24 bits, the program addressing range can reach 16M, the data bus is 32 bits, and the internal memory has 34K ×32bit SRAM can be mapped in the program or data space as needed. It has a serial port that can transmit 8, 16, 24, and 32-bit data. Its transmission mode can be set to burst mode or continuous mode. Two 32-bit general-purpose timers can be used to communicate with the chip internally or with the outside at specified time intervals.

　　Considering that this system is mainly used in ADC, it directly uses the data bus and address bus of TMS320VC33 without adding additional circuits, so that the sampling speed and conversion accuracy of ADC are well guaranteed. At the same time, the INT2 and XF0 pins are also used as the interrupt signal for DSP to receive data and the enable signal of ADC. INT2 is an external interrupt pin, which is triggered by external data input; XF0 is an external flag output pin, which is controlled by software and can be used to send signals to external devices. The status of this pin is determined by the I/O flag register, IOF =0X22, that is, XF0 is set as a general-purpose output pin, and the pin outputs 0; if IOF=0X26, XF0 is set as a general-purpose output pin, and the pin outputs 1. This system uses software instructions to set XF0 high and low to control the start, conversion and stop of the ADC.

　　EMP7512AE is based on EEPROM technology and uses multi-voltage I/O interface technology. The system core supply voltage is 3.3V, and the I/0 pin is compatible with 2.5V, 3.3V, and 5.0V logic levels. The EPM7512AE has 10,000 available gates, 512 macrocells, 32 logic array blocks, and 212 user-available I/0 pins. The main function of CPLD in the system is to provide clock signals for ADC conversion and control the enable and reset of ADC conversion. Since the ADC chip used is serial output, CPLD also realizes the conversion of serial data input into parallel data. output, and then directly connected to the data bus of TMS320VC33. At the same time, the CPLD generates a pulse signal. After the ADC conversion is completed, the data is temporarily stored in the CPLD. The pulse applies for an interrupt to the CPU, indicating that there is data that needs to be received. In addition, a key role of CPLD is to realize the dynamic selection of the number of channels. The maximum number of channels currently designed for the system is 8. The specific hardware connection diagram of CPLD, DSP and AD chip is shown in Figure 2.

System software design
　　In the software design, the ADC conversion is dynamically controlled through the CPLD program, the analog signal input terminal is gated, the ADC is enabled, and the data sampling and transmission of the MAX1162 is completed according to the conversion timing diagram shown in Figure 3.
The main program part of VHDL language is given below.

BEGIN
ADCS <= SYNTHESIZED_WIRE_12;
ADA <= SYNTHESIZED_WIRE_2;
GDFX_TEMP_SIGNAL_1 <= (L & L & H & H & H & L);
GDFX_TEMP_SIGNAL_0 <= (H & L & H & H & L);
U1 : lpm_bustri_0---- Three-state bus buffer, allowing sampled data to be output to the DSP data bus
PORT MAP (enabledt => DRD,
data => ADO,
tridata => D);
U2: lpm_counter_1----counter, change the data bus width For 3-bit
PORT MAP(sload => SYNTHESIZED_WIRE_0,
clock => SYNTHESIZED_WIRE_1,
aload => XFA0,
data => CMD(2 downto 0),
q => SYNTHESIZED_WIRE_2);
U3: lpm_dff_1---D flip-flop, data bus width It is 8 bits and receives data from DSP
PORT MAP(clock => CMDCK,
data => D(7 downto 0),
q => CMD);
U4: lpm_compare_1---comparator, compare CMD(5..3 ) and the value of CMD(2..0), that is, polling sampling channel
PORT MAP(dataa => CMD(5 downto 3),
datab => SYNTHESIZED_WIRE_2,
aeb => SYNTHESIZED_WIRE_0);
SYNTHESIZED_WIRE_1 <= NOT(AQ(4) );
NRW<= NOT RW;
CMDCK<= NOT( NOT PAGE3 AND(NOT RW)AND A6 AND A5 AND A4 AND (NOT A3));
----Channel control address encoding
DRD <= NOT PAGE3 AND RW AND A6 AND A5 AND A4 AND A3;----Sampling address encoding
CLKA <= NOT(CLK);
U5: lpm_counter_2---Generate count pulse
PORT MAP(sload => SYNTHESIZED_WIRE_3,
clock => HFP(5),
data => GDFX_TEMP_SIGNAL_0,
eq => SQ,
q => AQ);
U5 : lpm_dff_5---buffer
PORT MAP(clock => SYNTHESIZED_WIRE_12,
data => SYNTHESIZED_WIRE_5,
q => ADO);
SYNTHESIZED_WIRE_12 <= SQ(12) OR 0 OR XFA0;
SYNTHESIZED_WIRE_3 <= <=
NOT (HFP (2)); SYNTHESIZED_WIRE_6 <= NOT(HFP(3)); INTA2 <= XFA0 OR SYNTHESIZED_WIRE_9; U6:








U7: lpm_counter_3---Generate clock signal
PORT MAP(sload => SYNTHESIZED_WIRE_10,
clock => H1CK,
data => GDFX_TEMP_SIGNAL_1,
q => HFP);
SYNTHESIZED_WIRE_8 <= NOT(HFP(1));
ADSCK <= NOT(HFP (5));
SYNTHESIZED_WIRE_9 <= NOT(SYNTHESIZED_WIRE_12);
H <= '1';
L <= '0';
END;

　　After writing this VHDL program into the EPM7512AE chip, it will be much simpler to program the data sampling . Add ADPORT in the MEMORY section of the .CMD file: org=0x00c00070, len=9. Then map the array adport[8] to the segment ADPORT through the custom data segment. The main sampling program written in C is given below.
Main()
{
......
IOF = 0x26;/*Set the MAX1162 data output terminal to a high-impedance state*/
adport[0] = 0x28;
/*Sampling channel selection: channel 0~5, a total of 6 channels; if set adport[ 0]=0x38, then the channels are: channel 0~channel 7, a total of 8 channels. In the same way, other settings can be made*/
IE = 4;/*Interrupt enable*/
IOF = 0x22;/*Start ADC*/
/* The corresponding address of adport[0] is 0x00c00070, and the configuration register has 6 bits, 0, 1, Bit 2 corresponds to the starting channel, and bits 3, 4, and 5 correspond to the ending channel. The corresponding address of adport[8] is 0x00c00078, which is the control register*/
...
}

　　The sampled data is received in the interrupt service subroutine. The program is as follows.
C_INT02()
{
ad[adi++] = adport[8];/*Save the collected hexadecimal data into the array ad*/
If(adi>0x7ff) /*The size of the stored data is 2K×16bit, Dynamically changes according to the memory size */
adi &= ox7ff;
}

Conclusion
　　After actual verification, the sampling accuracy of this ADC system reaches 13 bits at low cost, which reaches a very good level among 16-bit ADC chips, and Be applied to high-precision industrial control. Using TMS320VC33 and EPM7512AE, the control and dynamic multi-channel sampling of the high-precision analog-to-digital converter MAX1162 can be flexibly and conveniently realized, simplifying the complexity of the system design and making the DSP programming process very efficient and concise. If applied to scenes with more stringent requirements, this system needs to be further improved. The ADC chip should be replaced with parallel output, the CPLD chip should be replaced with CycloneII FPGA, the DSP chip should be TMS320C6713, and a noise suppression design should be added. In this way, the performance of the entire system will be improved. will be significantly improved. Under certain conditions, similar to the ADC module, this system can be expanded to achieve more channels of signal collection.

References
1 Xu Huimin, Ande Ning, editors. Digital logic design and VHDL description. Machinery Industry Press, 2004
2 Zhang Xiongwei et al. DSP integrated development and application examples. Electronic Industry Press, 2002
3 MAX1162,16-Bit,+ 5V,200ksps ADC with 10μA Shutdown.MAXIM
4 TMS320VC33 DIGITAL SIGNAL PROCESSOR, Texas Instruments Incorporated