Design of Power Factor Correction AFPC Circuit Based on MC33262

The APFC system introduced in this paper uses the MC33262 dedicated integrated circuit control chip produced by Motorola, USA, and makes it work in critical conduction mode (CRM).

1 Introduction to APFC principle based on MC33262

The topology circuits used to realize APFC converters include Boost converters, flyback converters, and Boost-Buck converters. However, Boost circuits are most widely used because they have the following special advantages: input inductance, which can reduce the requirements for input filtering; the voltage of the switching device does not exceed the output voltage value; and they are easy to drive . The design here is mainly based on the Boost converter.

At present, there are many control chips for realizing critical conduction mode, and the APFC circuit using Boost converter is composed of MC33262. The principle block diagram of MC33262 is shown in Figure 1.

In Figure 1, pin 5 is the zero current detection input terminal, which is connected to the secondary side of the transformer, so what is detected is the inductor current, that is, the current flowing into the load from the external power supply . When the inductor current is zero, the output of ZCD flips, sets the internal RS trigger to "1", and pin 7 outputs a high level, turning on Q1. The external power supply uses bridge rectification to turn on the primary side of the transformer and Q1, and the current flows through the primary side of the transformer, storing electrical energy in the inductor. When the inductor current increases to a certain value, Q1 is turned off again, which is also controlled by the RS trigger. Pin 1 is connected to the divided voltage of the PFC output voltage. After the voltage is amplified by EMP, it is multiplied by the voltage divided value input from pin 3 in MULT, and the output of MULT is compared with the current of Q1 input from pin 4.

When the current value of the input Q1 is greater than the current value of the MULT output, the OIC output level flips, and the RS trigger is set to "0". This level is output from pin 7, turning off Q1. Therefore, the output current of MULT is the threshold value of the current passing through Q1, and this threshold value changes approximately sinusoidally with the change of the input voltage. When Q1 is turned off, the current on the primary side of the transformer gradually decreases. When this current approaches zero, it causes the output of ZCD to flip, and the RS trigger is set to "1", Q1 is turned on, and the above process is repeated.

When the load is suddenly turned off or started, or a surge occurs at the output, the output voltage will be too high, and OVC will play a protective role. At this time, the output level of the overvoltage protector is reversed, and the RS trigger is set to "0", turning off Q1. The comparator threshold voltage set in the device is 1.08 V. The function of undervoltage lockout is to monitor the positive voltage of the power supply. When the voltage Vcc at pin 8 is lower than the lower limit, UVLO outputs a low level, and pin 7 also outputs a low level, turning off Q1. The function of the timer is to start Q1 when the inductor current drops to zero.

2 Design of main technical indicators of the system

According to the needs, a 150 W PFC system is designed, and its signal flow and signal waveform are shown in Figure 3. Its main parameters are: AC input voltage range is 175~265V; maximum output power is 150 W, if the boost voltage of the Boost circuit is 400 V, the rated DC current is 375 mA; if the conversion efficiency is η=90%, the rated input power Pin=P0/η=167 W; the minimum switching frequency is selected as fmin=25 kHz; the input offset factor IDF=0.98; the maximum ripple peak-to-peak value is 8 V.

3 Calculation of main circuit parameters

3.1 Calculation of inductance L

The required inductance value under the lowest operating frequency condition can be calculated by formula (1):

Where: Vin is the maximum value of the peak voltage of the regulated input; Pin is the maximum value of the input power; fmin is the minimum value of the switching frequency. Substituting the main parameters into formula (1) we get:

L=544μH, in this design L=550μH.

3.2 Input filter capacitor design

The main function of the input filter capacitor is to filter out the high-frequency noise at the input end, and its capacity is very small. However, if its value is too small, it is difficult to filter out the high-frequency noise at the input well. On the other hand, its value cannot be too large, otherwise it will cause a large input voltage offset.

3.2.1 Lower limit of input filter capacitor

The lower limit of the input filter capacitor is determined by the maximum ripple voltage of the input filter capacitor and can be calculated using formula (2):

Where: △Vcin(max) is the maximum ripple voltage of the filter capacitor. Generally, this value can be less than 5% of the minimum input voltage peak. Substituting the main parameters into formula (2) yields:

3.2.2 Lower limit of input filter capacitor

The upper limit of the input filter capacitor is determined by the input offset factor IDF, which can be calculated using the following formula:

The selection of output capacitors should not only consider the capacitance, but also the voltage stress. Since the circuit has a slow response speed, when the load suddenly becomes lighter, it may cause an overshoot of the output voltage. Considering a certain margin, its withstand voltage can be selected to be greater than the output overvoltage protection point 1.1VOVP. In this circuit design, an electrolytic capacitor with Co=220μF and a withstand voltage of 450 V is selected.

3.4 Selection of power switch tube and output diode

The current stress and voltage stress of the power switch tube and the output diode are the same. The current stress and voltage stress of the two are calculated separately below. The maximum peak current of the switch tube and the diode is:

The voltage stress of the switch tube and the output diode needs to consider the output overvoltage protection point, so its maximum voltage is:

In this circuit design, the power field effect tube IRF84.0 is selected as the switching tube, whose withstand voltage is 500 V and the maximum current is 8 A; the fast recovery diode MURl560 is selected as the output diode, whose withstand voltage is 600 V and the maximum current is 15 A.

4 Experiments and Conclusions

The experimental results (see Figures 4 to 7) show that the AC/DC converter can achieve a highly stable DC voltage output of 400 V in a wide input voltage range; the ripple peak-to-peak value is below 8 V; the output rated power is 150 W; the efficiency η=95% under full load; the power factor λ≥0.99; and the input current total harmonic distortion D<6%. At present, this controller with APFC circuit has been applied to electronic ballast products.

5 Conclusion

The power factor correction circuit composed of MC33262 has a simple peripheral structure, few circuit components, reduced circuit size and cost, and improved system reliability. At present, this APFC technology has been applied in many fields such as switching power supplies and electronic ballasts. The APFC circuit adopts peak current control mode, which belongs to quasi-continuous current mode. The MOS-FET switching frequency is very high, which has high requirements for the design of EMI filter circuits. However, compared with other APFC chips using continuous mode, this series of chips has a higher cost performance and is worthy of further improvement and research.