Design of Three-Phase Function Signal Generator Based on FPGA

The FPGA - based three-phase function signal generator uses DDS as the core, and realizes the generation of sine wave, square wave, triangle wave and sawtooth wave signals on Altera's CycloneⅡ series EP2C8T144C8. The single-chip microcomputer PICl8F4550 controls the frequency and phase difference of the waveform. At the same time, the single-chip microcomputer controls the waveform data conversion DAC902 reference voltage through DAC0832 to achieve the control of the waveform amplitude. The waveform output by D/A is amplified and filtered before output. The input and output of waveform parameters are realized through the touch screen and LCD screen. The test results show that the system has high accuracy and stability.

Analog The output waveform of the function signal generator is easily affected by the input waveform, and it is difficult to achieve phase shift control. The phase shift angle drifts with the influence of factors such as the connected load and time. The adjustment of frequency and amplitude depends on the potentiometer, so the accuracy is difficult to guarantee and it is difficult to achieve satisfactory results. The digital three-phase signal generator based on FPGA has high accuracy and convenient phase shift control. It can achieve a frequency of 1 Hz to 10 MHz, an amplitude of 0.1 to 10 V, a resolution of 1°, and a three-phase function signal generator with programmable frequency and amplitude. The system also has the advantages of flexible output and easy system upgrade.

1 Principle of function signal generator

Based on the principle of DDS, the frequency control word M and the phase control word P control the frequency and phase of the DDS output waveform respectively. The phase accumulator is the core of the entire waveform generation. It consists of an accumulator and an N-bit phase register. With each clock pulse, the phase register increases in step size M, as shown in Figure 1. The output of the phase register is added to the phase control word, and the result is used as the address of the waveform lookup table. The waveform lookup table is composed of ROM, which stores the digital amplitude information of a complete cycle of the waveform. Each search address corresponds to a phase point in the range of 0° to 360° in the waveform. The address information input to the lookup table is mapped to the waveform amplitude signal and output to the input section of the digital-to-analog converter at the same time. The analog signal output by the DAC passes through the programmable filter to obtain a waveform with a pure spectrum.

The phase register returns to the initial state after every 2N/M fc clock cycles. Correspondingly, the waveform lookup table returns to the initial position after one cycle, and the DDS outputs a waveform. The output waveform period is Tout=(2N/M)Tc, and the frequency is

The minimum resolution of DDS is fmin=fc/2N. When M=2N-1 (that is, only two points are taken in one cycle), the highest fundamental wave synthesis frequency of DDS is foutmax=fc/2. According to the sampling theorem, this is theoretically feasible. Taking into account the distortion problem, i (i>2) points are taken, then the highest frequency is when M=2N-3, foutmax=fc/i.

2 Overall system design

The system consists of a single-chip control module, an FPGA waveform generation module, a digital-to-analog conversion module, a filter output module, a touch screen input and a liquid crystal display module. The single-chip controls the FPGA to generate three-phase sine waves, square waves, triangle waves and sawtooth waves with input frequency and phase difference, and the three-phase waveforms are filtered and output after D/A conversion. The amplitude of the three-phase waveform is also controlled by the single-chip by changing the reference voltage of D/A. The specific system block diagram is shown in Figure 2.

The specific block diagram of the FPGA part is shown in Figure 3. Based on the DDS principle, it is mainly composed of a phase accumulator, a sine wave ROM lookup table, a square wave generator, a triangle wave generator, a sawtooth wave generator, and a waveform selection module. The phase difference of the three-phase waveform is adjusted according to the phase shift value set by the microcontroller, and the waveform selection is also controlled by the microcontroller.

2.1 Frequency division module design

In order to accurately control the waveform frequency, different frequency bands require different input frequencies. In the project design, a 50 MHz external active crystal oscillator is used, and the frequency is locked at 40.96 MHz using the internal phase-locked loop of the FPGA. Then the frequency is 10 MHz, 100 MHz, 1 000 MHz, and 10 000 MHz, as shown in Figure 4. In this way, 5 different frequency intervals are obtained. Finally, the required clock frequency is selected by the microcontroller through the 5-to-1 data selector. The specific relationship between the clock frequency and the output waveform frequency is shown in Table 1.

2.2 Waveform generation module design

2.2.1 Sine Wave

The sine wave data needs to be converted into a *.mif file and stored in the ROM. The mif file has a fixed format that specifies the bit width WIDTH of each word, the total number of words DEPTH, the address base ADDR-ESS_RADIX and the data base DATA_RADIX. The sine wave data is calculated by programming in the Matlab environment, and then the mif file is generated.

EP2C8T144C8 has ample storage space. Therefore, in order to improve the accuracy, 4096 sinusoidal data are stored in ROM in the design. The frequency control word and phase control word are generated by the microcontroller, and the address generator is composed of the phase accumulator. The generated address is connected to the address line of ROM to look up the table to obtain the waveform data.

2.2.2 Square wave

The square wave algorithm is relatively easy to implement. Since it has only two states, high and low level, it only needs to flip the level in the middle of a cycle. Since the value of the phase accumulator is accumulated linearly, the value of the address address is also accumulated linearly. The given address value address is judged. When the highest bit of the address value is 0, the waveform amplitude is assigned 1 to each word bit, otherwise it is assigned 0. The simplest square wave with a duty cycle of 50% can be realized.

In order to realize the adjustable duty cycle, a variable PWM_zkb[11． ． 0] is added in the design to compare the address value with WM_zkb[11． ． O].

2.2.3 Triangle wave

The principle of generating a triangle wave is similar to that of generating a square wave. The value of the address Address is also judged. When the highest bit is 0, the 0~11 bits are taken as the waveform amplitude of the triangle wave, that is, Data_out[11．．0]=Address[11．．0]. When the highest bit is 1, the value of the 0~11 bits is inverted and used as the waveform amplitude of the triangle wave, that is, Data_out[11．．0]=not(Address[11．．0]).

2.2.4 Sawtooth Wave

The generation of sawtooth wave is also based on the above principle. It is to judge the value of address Address. When its highest bit is 0, its 0~11 bits are taken as the waveform amplitude of triangle wave, that is, Data_out[11．．0]=Address[11．．0]. When its highest bit is 1, the value of its highest bit is inverted and used as the waveform amplitude of sawtooth wave, that is, Data_out,[11．．0]=Address[11．．0]and "011111111111".

2.3 Implementation of Phase Shift

On the basis of the A-phase address, an accumulator is added, and the input segments are the A-phase address and the offset value. After accumulation, the B-phase waveform address is obtained, and then the ROM is addressed according to this address or a square wave, a triangle wave and a sawtooth wave are generated based on the address. As shown in Figure 5, the offset between the A-phase, the B-phase and the B-phase, the C-phase is controlled by the microcontroller, and the data is sent to the accumulator after being latched.

2.4 Implementation of waveform selection

According to the design requirements, each phase can output any waveform such as sine wave, square wave, triangle wave and sawtooth wave. A 4-to-1 data selector is designed, and the control terminal Sel[1. -. 0] is connected to the IO port of the microcontroller, as shown in Figure 6, taking phase A as an example.

2.5 Implementation of Amplitude Control

The reference voltage can be selected as internal or external through the INT/EXT terminal. When the port is high, the external reference voltage is selected. As long as the reference voltage is changed, the amplitude of the output waveform can be changed. The external reference voltage range of DAC902 is 0.10~1.25 V, so only an 8-bit D/A is needed to achieve a step of 0.01 V. As shown in Figure 7, the DAC0832 output is connected to the DAC902 reference voltage input terminal REFin, and the DAC0832 output is controlled by the microcontroller, thereby controlling the DAC902 reference voltage.

3 System Testing

The waveform parameter setting of this system is completed through touch screen input. The output waveform under 50 Ω load is tested with an oscilloscope to compare the error between the set value and the test value. Figure 8 shows the output waveform of the sine wave taken by a digital camera in the "Analog" mode of the Fluck PM3394B 200 MHz Combiscope Instrument when the output frequency of the signal source is 10 MHz, the peak-to-peak value is 5 V, and the phase shifts of the two signals are 45°, 90°, 180°, and 270° respectively.

After many tests and repeated improvements, the following technical indicators were finally achieved:

(1) Output waveform: sine wave, square wave, triangle wave, sawtooth wave.

(2) Output waveform frequency range: 0.1 Hz ~ 10 MHz.

(3) Output frequency adjustment step: 0.01 Hz ~ 10 kHz.

(4) Output voltage range: 10 mV to 10 V (peak-to-peak), adjustable, with a minimum amplitude step of 10 mV.

(5) Square wave duty cycle adjustment range: 1% to 99%.

Since an oscilloscope has only two channels, it can only measure the phase difference between the two signals.

In terms of frequency stability, the output waveforms of sine wave, triangle wave, square wave and rectangular wave are stable, which reflects the characteristics of DDS technology. The output frequency stability is at the same order of magnitude as the crystal oscillator stability. Due to the use of the internal clock of the FPGA, the calculated clock cannot be reached after the frequency multiplication and division, so there is an error, but the error is slightly more obvious in the higher frequency part. Therefore, software correction is used in the design to reduce the error in the higher frequency part.

As for the control of the waveform amplitude, since the waveform has a certain attenuation in the circuit network, software compensation is used in the program to correct it. From the test results, it can be seen that the more detailed the software compensation is, the smaller the error is.

4 Conclusion

This project takes multi-function, low power consumption, easy operation, reasonable structure and easy debugging as the main design principles. During the system design process, we strive to keep the hardware circuit simple, give full play to the convenient and flexible software programming features, and maximize the FPGA chip resources to meet the system design requirements.

Using hardware description language VHDL programming, Ahera's Quartus II software environment was used for compilation and simulation testing. A function generator was designed on the FPGA chip to generate sine waves, triangle waves, square waves and other waveforms. The system has high frequency resolution and fast frequency switching speed. The design uses EDA technology to shorten the development cycle, improve design efficiency, and make the system compact, flexible in design, simple to implement, and stable in performance.