Digital tube drive display circuit designed by CPLD

Digital tube driver display circuit designed by CPLD

1.1 Display principle:

The eight-segment digital display tube is shown in Figure 1.1. Each segment of the eight-segment digital tube is a light-emitting diode, and there are eight light-emitting diodes a to g and the decimal point dp. The cathodes of each diode in the eight-segment digital tube are connected in parallel to form a common cathode terminal. In this way, the common cathode pin is grounded. At this time, whichever pin inputs a high level, the corresponding light-emitting diode will be lit.

Figure 1.1 Eight-segment digital display tube

The pin diagram of the CL5461AS digital tube is shown in Figure 1.2. It connects the a~g and decimal point dp pins of the four digital display tubes in parallel as the digital tube data input terminal; and leads out the cathodes A1~A4 of each digital tube respectively.

Figure 1.2 CL5461AS digital tube pin diagram

As long as the frequency of the A1~A4 pins is greater than 40Hz, the visual effect of four digital tubes being lit at the same time can be achieved. By inputting different data while lighting different digital tubes, four different numbers can be displayed on the digital tubes at the same time. For example: four digital tubes are to display the number 9876. The first digital tube A1 is added with a low level, and the rest A2, A3, A4 are high levels, and the digital tube inputs the data corresponding to 9; then the second digital tube A2 is added with a low level, and the rest A1, A3, A4 are high levels, and the digital tube inputs the data corresponding to 8; then the third digital tube A3 is added with a low level, and the rest A1, A2, A4 are high levels, and the digital tube inputs the data corresponding to 7; then the fourth digital tube A4 is added with a low level, and the rest A1, A2, A3 are high levels, and the digital tube inputs the data corresponding to 6; repeat the above process over and over again, and the four digital tubes will display the number 9876.

1.2 Driving eight-digit digital tube display circuit diagram

Use CPLD to design a circuit to drive an 8-bit digital tube display. The pin diagram of the 8-bit digital tube is shown in Figure 1.2.

Use two CL5461AS digital tubes to form an eight-digit digital tube display, connect the a~g and decimal point dp pins of the two CL5461AS digital tubes in parallel, and the cathodes A1~A4 of the two CL5461AS digital tubes are defined as Vss0, Vss1, Vss2, Vss3, Vss4, Vss5, Vss6, and Vss7.

The block diagram of a circuit for driving an eight-bit digital tube display using CPLD is shown in Figure 1.4.

Figure 1.4 Block diagram of the circuit driving the eight-bit digital tube display

The output of the clock pulse counter is also used as the input of the 3-line to 8-line decoder and the eight-to-one data selector address code.

The output of the clock pulse counter is decoded by a 3-line to 8-line decoder, and its output signal is connected to the cathode Vss0, Vss1, Vss2, Vss3, Vss4, Vss5, Vss6, and Vss7 of the eight-bit digital tube. Which of the data information A to H to be displayed is selected by the address code of the eight-choose-one data selector, and the selected data information is decoded by the seven-segment decoder and connected to the a to g pins of the digital tube. In this way, the eight digital tubes can display eight numbers in turn. If the clock pulse frequency is appropriate, the visual effect of eight digital tubes being lit at the same time can be achieved.

1.3 Modules and module functions:

1.3.1 Clock Pulse Counter Module

The clock pulse counter module CN8 is shown in Figure 1.5. The input signal of the CN8 module is the clock pulse clk, whose frequency is greater than 40Hz. Every time a clock pulse clk rises, the internal accumulator is incremented by one, and the result of the accumulator is output in the form of a binary number. To display eight digits, a three-digit binary number is used as the output. The output signal is cout[0..2].

Figure 1.5 Clock pulse counter module CN8

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity cn8 is

port(clk:in std_logic;

cout:out std_logic_vector(2 downto 0));

end cn8;

architecture rtl of cn8 is

signal q: std_logic_vector(2 downto 0);

begin

process(clk)

begin

if (clk'event and clk='1' ) then

if (q=7) then

q<="000";

else

q<=q+1;

end if;

end if;

end process;

cout<=q;

end rtl;

1.3.2 3-8 Line Decoder Module

The 3-8 line decoder module DECODER3_8 is shown in Figure 1.6. The input terminal of the DECODER3_8 module is A[2..0], which receives the output signal of the clock pulse counter CN8 module. After decoding, the output signal Q[7..0] is connected to the cathodes of the eight digital tubes Vss7, Vss6, Vss5, Vss4, Vss3, Vss2, Vss1, and Vss0 respectively, so that the cathode of the corresponding digital tube is low level and the corresponding digital tube is lit. To display eight digits, eight output terminals are required, so a 3-8 line decoder is made.

Figure 1.6 3-8 line decoder module DECODER3_8

library ieee;

use ieee.std_logic_1164.all;

entity decoder3_8 is

port(a:in std_logic_vector(2 downto 0);

q:out std_logic_vector(7 downto 0));

end decoder3_8;

architecture rtl of decoder3_8 is

begin

process(a)

begin

case a is

when "000"=>q<="11111110";

when "001"=>q<="11111101";

when "010"=>q<="11111011";

when "011"=>q<="11110111";

when "100"=>q<="11101111";

when "101"=>q<="11011111";

when "110"=>q<="10111111";

when thers=>q<="01111111";

end case;

end process;

end rtl;

1.3.3 Eight-choice data selection module

The eight-choose-one data selection module SEL81 is shown in Figure 1.7. The input signal of the SEL81 module is the address code SEL[2..0] of the data selector SEL81, and the other part is the data information A[3..0] ~ H[3..0]. The address code SEL[2..0] comes from the clock pulse counter CN8, and the address code SEL[2..0] determines which input data is output. The output signal is Q[3..0].

Figure 1.7 Eight-choice data selection module SEL81

library ieee;

use ieee.std_logic_1164.all;

entity sel81 is

port(sel:in std_logic_vector(2 downto 0);

a,b,c,d,e,f,g,h:in std_logic_vector(3 downto 0);

q:out std_logic_vector(3 downto 0));

end sel81;

architecture rtl of sel81 is

begin

process(a,b,c,d,e,f,g,h,sel)

variable cout: std_logic_vector(3 downto 0);

begin

case (sel) is

when "000"=>cout:=a;

when "001"=>cout:=b;

when "010"=>cout:=c;

when "011"=>cout:=d;

when "100"=>cout:=e;

when "101"=>cout:=f;

when "110"=>cout:=g;

when thers=>cout:=h;

end case;

q<=cout;

end process;

end rtl;

1.3.4 Seven-segment decoder module

The seven-segment decoder module DISP is shown in Figure 1.8. The DISP module is a seven-segment decoder that converts the input 4-bit binary number into the number corresponding to the digital display tube. For example, when the input is a 4-bit binary number 0000, in order to make the digital display tube display 0, the seven-segment decoder output is 0111111, that is, the g segment is 0, the g segment LED is off, and the other LEDs are lit, and the display effect is 0. The DISP module input signal D[3..0] is connected to the output signal Q[3..0] of the eight-choice data selection module; the seven-segment decoder output signal Q[6..0] is connected to the a~g pins of the digital tube.

Figure 1.8 Seven-segment decoder module DISP

library ieee;

use ieee.std_logic_1164.all;

entity display is

port(d:in std_logic_vector(3 downto 0);

q:out std_logic_vector(6 downto 0));

end disp;

architecture rtl of display is

begin

process(d)

begin

case description

when"0000"=>q<="0111111";

when"0001"=>q<="0000110";

when"0010"=>q<="1011011";

when"0011"=>q<="1001111";

when"0100"=>q<="1100110";

when"0101"=>q<="1101101";

when"0110"=>q<="1111101";

when"0111"=>q<="0100111";

when"1000"=>q<="1111111";

when thers=>q<="1101111";

end case;

end process;

end rtl;

1.3.5 Overall circuit for driving eight-digit digital tube display

Connect each module to form a whole Circuit diagram As shown in Figure 1.9, the function of designing a circuit to drive an eight-digit digital tube display can be realized by using CPLD. clk is the clock pulse input signal. After passing through the clock pulse counter CN8 module, the signal is output in the form of a 3-bit binary number. The output signal is COUT[2..0]. The output of the clock pulse counter CN8 is also used as the input of the 3-line-to-8-line decoder DECODER3_8 and the eight-to-one data selector SEL81 address code SEL[2..0]. The output of the clock pulse counter CN8 is decoded by the 3-line-to-8-line decoder DECODER3_8, and its output signal Vss[7..0] is connected to the cathode Vss7, Vss6, Vss5, Vss4, Vss3, Vss2, Vss1, and Vss0 of the eight-digit digital tube to determine which digital tube is lit. At the same time, the signal output by the clock pulse counter CN8 module also enters the input of the data selector SEL81 address code SEL[2..0] to select the output data, and its output is Q[3..0]. The output of the eight-choose-one data selector SEL81 module is Q[3..0], which is then translated into data that can be used by the digital display tube through the seven-segment decoder DISP module. The output Q[6..0] of the seven-segment decoder DISP module is connected to the a~g pins of the digital display tube through 300 ohm resistors . The input end of the eight-choose-one data selector module can be designed according to specific needs.