Design and implementation of signal processing circuit for non-gyro north finder

High-precision north finders can be divided into two categories: traditional gyro north finders and non-gyro north finders. The method of using gyroscopes to find the north is limited by the accuracy and cost of the gyroscope itself, and it is difficult to achieve high accuracy and low cost at the same time. The use of high-precision accelerometers to develop non-gyro north finders can break through this limitation and achieve high-precision, automated, and rapid north finding, thus becoming a new technical direction for north finder research. Many references have conducted a lot of simulation research on the north-finding principle and signal processing methods, but there are few studies on the specific implementation of the circuit. This article designs the circuit structure of the north finder.

1 Non-gyroscopic north-seeking principle
The principle of non-gyroscopic north-seeking is to install an accelerometer on a constant-speed turntable, with a certain tangent point on the edge of the turntable as the reference point (relative motion), and its tangential velocity and the north component of the earth's rotational angular velocity form a composite motion to produce Coriolis acceleration. Through the dynamic modulation of the turntable, the Coriolis acceleration generated by the composite of the north component of the earth's rotational angular velocity and the tangential velocity at this point is output as a sinusoidal signal. The phase corresponding to the peak value of the sinusoidal signal is detected by a high-precision quartz flexible accelerometer, which is the true north direction of the location on the earth, thereby achieving north-seeking. Its basic principle is shown in Figure 1.

Assume that the rotation speed of the turntable is Ω, the measuring axis IA of the accelerometer is vertically upward, the eccentricity from the turntable axis is ρ, and ωN is the north component of the earth's velocity.
The actual output of the accelerometer is:
a=f+FMcos(Ωt-ψ)+ω (1)
Where: f=-g+a0, a0 is the zero bias of the accelerometer, g is the acceleration of gravity; ω is the output noise; FM=2ΩoωN, is the maximum Coriolis acceleration; ψ is the initial azimuth of the turntable.
The DC part of the above signal can be filtered out by an AC amplifier. It is known that 10 and ωN are constants; in addition, the encoder and the motor are closed-loop through a phase-locked loop to keep Ω constant, so FM is a constant. Using the encoder's reference pulse, the sinusoidal signal is synchronously detected to calculate the initial azimuth ψ. Assume:

2 Circuit design and implementation
2.1 Circuit design principle
The north-seeking system uses a high-precision quartz flexible accelerometer with a resolution better than 1×10-5 as a detection sensor, and the corresponding signal processing overall block diagram is shown in Figure 2. In order to realize real-time data processing, the orthogonal transformation and digital filtering circuit are completed using a dedicated digital signal processing chip.

2.2 Circuit implementation
2.2.1 High-precision I/V conversion
The output of the selected quartz flexible accelerometer is a current signal with a scale factor of 1.3 mA/g. Therefore, an I/V conversion circuit is required to convert the measured weak current signal into a voltage signal. The output signal of the I/V conversion circuit contains two parts, DC and AC, and only the AC signal is useful. It is necessary to further use an AC amplifier for voltage amplification to isolate the DC component (i.e., the zero bias and gravity acceleration of the accelerometer) and amplify the AC signal.
2.2.2 Design of bandpass filter
The rotation speed of the turntable is 900 r/min, so the frequency of the useful signal actually output by the accelerometer is 15 Hz. In addition to the useful signal, the sampled data also contains low-frequency components below 15 Hz, integer multiple frequency signals, and non-integer multiple frequency signals, etc., which are relatively large noises. Secondly, the signal will also generate noise signals when it passes through the conductive slip ring, transmission cable, and operation processing circuit. In order to improve the signal-to-noise ratio of the line, a high-Q bandpass filter is designed for filtering.
Ordinary active filters are difficult to adjust parameters, have poor stability, are difficult to achieve narrow bandwidth design, and are not easy to obtain high Q values. Here, the MAX260 integrated active filter is used to design a bandpass filter.
MAX260 is a CMOS dual second-order universal switch active filter that can form various bandpass, low-pass, high-pass, notch and full-pass configurations without external components. The center frequency f0, quality factor Q and filter working mode can be set under program control. The chip uses a 24-pin DIP or SO package, has four working modes and their own clock inputs and independent f0 and Q control. Connecting in the manner of Figure 3 can form a fourth-order active filter. The filter design can be achieved by using a computer combined with the design software provided by Maxim to set the chip functions and various parameters.

2.2.3 Design of A/D conversion and orthogonalization circuit
Figure 4 is a basic model of digital orthogonal demodulation circuit. The input analog intermediate frequency signal is first converted by A/D to realize digital sampling. Its data stream is divided into two paths and multiplied by the cos component and sin component generated by the local digital oscillator (NCO) respectively through the digital multiplier to realize the orthogonal transformation of the input signal.
Figure 5 shows a digital demodulation circuit used in vector signal analyzer, which consists of a 12 b output A/D conversion chip ADS809, a digital mixer HSP45116 and two low-frequency digital filters HSP43220, as well as DDS clock circuit and two FPGA control and chip initialization circuits.

The input signal s(t) is first digitized by ADS809. The data stream after A/D sampling enters the digital mixer HSP45116. The data stream is divided into two paths in the chip and multiplied with the output of the digital oscillator to achieve orthogonal transformation. HSP45116 is a high-performance digital mixer with a maximum operating clock frequency of 33 MHz. It contains a digitally controlled oscillator (NCO) with two orthogonal outputs and a 16-bit high-speed multiplier/accumulator. Figure 6 is a simplified block diagram of the HSP45116.

It can be seen that the chip functions are divided into three main parts: phase/frequency control, sin/cos oscillator and multiplier/accumulator (CMAC). Phase/frequency control is realized by the external control bus through FPGA to set the phase step value to realize the frequency control of NCO, and the phase accumulator is 32 bits. The phase accumulator takes the high 20 bits output as the address to look up the sin/cos table, so the NCO generates two orthogonal components sin and cos. In the circuit, in order to realize the orthogonal demodulation of the intermediate frequency signal, the signal is input from Rin and Iin is set to 0.
The system clock is formed by DDS (direct digital synthesis), which can realize the change of clock frequency and phase with a smaller resolution. Because the sampling rate of the I-channel and R-channel output signals is an integer multiple of the symbol rate of the measured modulation signal, in order to meet this requirement, the system clock is provided to the A/D converter, HSP45116 and HSP43220 at the same time. In addition, the system also includes FPGA, which is mainly used for initialization and control of HSP45116 and HSP43220.
The two digital signals output after the HSP45116 conversion are sent to the integrated digital filter HSP43220 for digital filtering. HSP43220 is a decimation digital filter (DDF) with linear phase characteristics. Its main application features are high-speed data input and low-speed output. DDF is implemented using a two-stage series filter structure. The combination of the two-stage filter can obtain a signal extraction capability of 16384. The signal output includes a 24 b signal data stream and a DATA RDY signal line. According to system requirements, the main role of HSP43220 in the system is three aspects: filtering out the second harmonic components generated by digital orthogonal mixing; flexible and wide range of decimation factor settings to solve the correlation problem between the output baseband signal sampling rate and the symbol rate; excellent low-pass characteristics and programmable passband frequency settings.
The filtered digital signal is sent to the FPGA. When the first zero-position signal output by the code disk arrives, the FPGA continuously reads the output data under the control line of the pulse frequency doubling signal output by the code disk and accumulates it. When the second zero-position signal output by the code disk arrives, the data acquisition and accumulation operation is stopped, and a data good signal is given, thereby realizing the integral operation. After the DSP reads the FPGA data good signal through the I/O port, it reads the data in the FPGA data register and calculates the azimuth of the zero position of the north-seeking instrument according to formula (4).

3 Conclusion
The detailed circuit design ideas and specific implementation process of the non-gyro north finder are given. The high-performance dedicated digital mixer HSP45116 and the integrated digital filter HSP43220 are used to realize the orthogonal operation and digital filtering of the accelerometer output signal in the non-gyro north finder. It has good signal mixing and orthogonal solution performance, which can not only overcome the inherent errors of analog circuits and system instability, but also reduce the calculation burden of DSP, meet the high precision and rapidity requirements of the non-gyro north finder, and thus make it possible to transform the non-gyro north-seeking technology from theoretical research to practical instrument equipment.