Design of high-speed data acquisition system for CCD cameras

Design of high-speed data acquisition system for CCD cameras

CCD (Charge Couple Device) is a semiconductor surface device that stores and transmits information in the form of charge packets. Due to the outstanding advantages of CCD cameras such as high sensitivity, low noise, and large dynamic range, it is widely used in scientific research fields such as astrophysics, aerospace, biological and medical research, X-ray imaging, underwater photography, molecular dynamics, and spectroscopy. At present, most of the domestic mid-to-high-end CCD cameras use image acquisition cards as a data transmission method, which has high requirements for computers and is inconvenient to maintain, which seriously hinders the development of CCD cameras. For this reason, this paper designs a data acquisition system for CCD cameras based on USB hot-swap and high data transmission rate.

1 Overall scheme of CCD camera data acquisition

The complete CCD camera system is relatively complex. A complete CCD camera system includes a cooling circuit, a CCD chip, a signal conditioning circuit, a timing drive and control circuit, a USB data acquisition and transmission module, etc. [1]. The overall scheme of CCD camera data acquisition is shown in Figure 1. This camera uses an independent cooling circuit (with temperature measurement and feedback control functions) to cool the CCD chip. This part of the circuit has nothing to do with the acquisition circuit. In order to avoid any impact, the two parts of the circuit are independent and do not share a common ground.



1.1 Signal conditioning circuit

In order to make the CCD output signal meet the requirements of the A/D converter input signal, this paper designs the CCD output signal conditioning circuit shown in Figure 2. The working principle is: the output signal U is amplified by the low-noise amplifier A1, then passes through the potentiometer W and the low-noise amplifier A2, and is subtracted from the output signal after the last reset in the A3 amplifier (SH1 is a sample and hold device, which holds the output signal in the A2 amplifier after the last reset), and then is held by the sample and hold device SH2 and amplified by A4 and output to the A/D converter. A3 is a differential amplifier, which realizes the subtraction of the current signal from the signal after the last reset, thereby eliminating the reset noise.



1.2 A/D conversion and control timing

The design of the analog-to-digital conversion circuit of the CCD output signal needs to be considered comprehensively. In particular, the resolution (number of bits of conversion output) and sampling and conversion speed of the converter are the main indicators that affect the entire system. At the same time, it is affected and restricted by the CCD readout signal, signal noise, and the complexity of computer image processing. A converter with too high performance cannot play its due role due to the constraints of other factors. Therefore, choosing a suitable A/D converter is the key to designing the conversion circuit. After the CCD adopts cooling measures, the thermal noise becomes very small. The reset noise can be reduced through the signal conditioning circuit. In order to give full play to the high signal-to-noise ratio advantage of the cooled CCD, a high-resolution A/D converter should be used. Taking into account the signal-to-noise ratio of the radiographic image, circuit noise, and cost, and referring to the situation of other CCD cameras, this paper selects the LTC1608CG analog-to-digital converter. It has an on-chip sample/hold, 16-bit resolution, and a conversion rate of 500 kS/s. Its speed, accuracy, and pipeline-free delay structure make the LTC1608 particularly suitable for high-speed multiplexed data acquisition systems [2].
The signal read out by CCD is converted into digital form by LTC1608 after passing through the preprocessing circuit. The start signal CON0 of A/D conversion is generated by the computer through the control circuit, and two 8-bit latches 74LS374 are selected. Under the control of the control circuit, the 16-bit data latched last time is transferred to the memory IDT7204. After the A/D conversion is completed, the next sampling is automatically performed and the BUSY signal is output. The BUSY signal is used to store the conversion result in the two latches, and then read into IDT7204 by the next control signal CON1. ​​The A/D conversion circuit diagram is shown in Figure 3. The timing diagram of CCD signal transfer, A/D control and data transmission control is shown in Figure 4.





1.3 FIFO

FIFO is a first-in-first-out data buffer. The difference between it and ordinary memory is that it has no external read and write address lines. It can only write and read data sequentially. Its data address is completed by the internal read and write pointer automatically adding 1, which makes it very simple to use. FIFO is generally used for data transmission between different clock domains. For example, one end of the FIFO in this article is LTC1608 data acquisition, and the other end is the USB data transmission interface of the computer. The A/D acquisition rate is 16 bit 500 kS/s, so the amount of data per second is 500 K×16 bit=8 Mb/s, and the transmission rate of the USB interface chip CY7C64613 used in this article is 12 Mb/s. FIFO can be used as a data buffer between two different clock domains. In order to ensure that data is written or read correctly without overflow or empty reading, it must be ensured that the FIFO cannot be written when it is full. Reading cannot be performed when it is empty. The working timing diagram of the FIFO chip IDT7204 in the design is shown in Figure 5.



1.4 USB data transmission

Because the USB interface supports plug-and-play, has advantages such as small size, system resource saving, reliable transmission, power supply, good compatibility, shared communication and low cost, the CCD camera using the USB interface is more convenient to transmit data with the host computer than using communication methods such as PCI, optical fiber and serial port, and has a higher transmission rate, which meets the requirements of modern communication. The key and focus of CCD cameras is to transmit data to the host computer through USB in real time, quickly and accurately. The USB interface of this CCD camera uses the CY7C64613 chip of Cypress Semiconductor Company. It is a fully integrated peripheral controller that supports USB2.0 protocol and contains enhanced 8051 core, rich ports and interrupt vectors, serial interface engine SIE, general programmable interface GPIF and other resources [3].

There are four types of processing when CY7C64613 is powered on. Here, an EEPROM with the first byte of 0xC0 is used for startup. When the chip is powered on, it is detected that the EEPROM with the first byte of 0xC0 is connected to the IIC bus. At this time, CY7C64613 automatically copies VID, PID and DID to the on-chip memory, and then CY7C64613 sends these data to the host. The host selects the appropriate firmware program according to the ID data and downloads it to the USB chip. After the initial enumeration is completed, the USB host driver chip is reset, and then CY7C64613 re-enumerates according to the user device, executes the internal firmware program, and realizes the initialization of the device and communication with the host. The EEPROM chip 24LC32A has the advantages of low power consumption, wide allowable operating voltage range, large capacity, support for IIC bus protocol, few I/O ports, convenient expansion, and simple reading and writing. Among them, WP is a protection pin. When it is high, only the device can be read, which is used for hardware data protection; when it is low, it can be read and written. The circuit diagram is shown in Figure 3, where since the SCL and SDA pins are open-drain and hysteresis inputs, an external 2.2 kΩ pull-up resistor must be connected.

This design uses a high-speed data transmission mode provided by the EZ-USB chip, namely the GPIF mode. It is an internal host control mode that uses internally integrated high-efficiency control logic to replace the external microcontroller to control the EZ-USB endpoint FIFO. In GPIF mode, in order to obtain the data in IDT7204, CTL0 is connected to the R pin, and the data is read from the external FIFO IDT7204 during each low-level period of R. RDY1 is connected to EF. If the external IDT7204 is empty, EF is low, and GPIF uses this pin to control the reading of data. The IDT7204 pointer automatically increases during the data transmission process. When the IDT7204 pointer is full, the data transmission is completed and enters the idle state. Otherwise, the data has not been completely transmitted. At this time, it is necessary to continue waiting for the data to be transmitted from the IDT7204. This ensures that the data in the IDT7204 is transmitted to the PC in real time and safely. The IDT7204 read waveform in GPIF mode is shown in Figure 6 [4-5].



2 Software Development

The development of the driver, application and firmware required for USB peripherals can use the development kit of CY7C64613 provided by Cypress. The driver develops USB devices by calling the functions in the host control function library CyAPI.lib based on the general driver CYUSB.SYS provided by Cypress. The firmware design can be implemented using the provided firmware package, which contains files such as fw.c, periph.c, lp.h, lpregs.h, etc., to implement services such as initialization of the EZ-USB chip, processing of USB standard device requests and USB suspend power management. After the firmware and driver are designed, they can be debugged using the EZ-USB Control Panel software provided by Cypress. The firmware workflow is shown in Figure 7.



The workflow of the host computer application software is shown in Figure 8. The application software can control the exposure time of the camera, refresh and resample the captured image, perform operations such as grayscale and contrast stretching and image noise reduction (filtering) on ​​the image, and can open and save the image in multiple formats.

The design of the CCD camera data acquisition system has completed a series of processes from overall scheme design to software and hardware debugging. The EZ-USB controller is used to realize the plug-and-play of the system, and the GPIF working mode is used to meet the data transmission bandwidth requirements of CCD high-speed data acquisition. After preliminary testing, its performance and indicators have met the expected requirements, laying a solid foundation for the future development of CCD cameras.