Application of Capacitor Error Averaging Technology in Pipeline ADC

1 Introduction

With the widespread application of digital signal processing technology in fields such as wireless communications, people have higher and higher requirements for the speed and accuracy of analog/digital converters (ADCs). However, due to power consumption and cost considerations, the reduction of device size and power supply voltage makes the design of high-speed and high-precision ADCs more and more challenging. Among various types of ADCs, pipeline ADCs have well coordinated the contradiction between area and speed. It has relatively low power consumption and chip size, and can achieve a higher conversion rate. However, when implementing high-resolution pipeline ADCs, if the errors caused by factors such as device mismatch (such as threshold offset caused by comparator voltage offset, capacitor mismatch, etc.) are not eliminated, they will have a serious impact on the performance of the ADC. Therefore, in order to reduce the error and enable the ADC to achieve higher effective accuracy to meet people's needs for high-precision modern data acquisition systems, many on-chip calibration technologies have been developed. Although these calibration technologies have their own characteristics, they can be generally divided into the following two categories: on-chip analog calibration; on-chip digital calibration. In addition, there is another important calibration technology - capacitor error averaging (CEA) technology. CEA technology has always been considered as a method of analog calibration, but the introduction of digital capacitor averaging technology in 2006 has made its existing implementation methods include both analog calibration and digital calibration. This article briefly introduces the principles and characteristics of various methods in capacitor error averaging technology, and thus looks forward to its development trend.

2 Structure of pipeline ADC

Although the actual pipeline ADC should be a fully differential structure, due to the symmetry of the circuit, this article only analyzes the principle of single-end (except for active error averaging technology). As shown in Figure 1, the entire circuit consists of a sample-and-hold circuit and N identical sub-stage circuits. The working principle of each sub-stage is the same:

(1) Sampling phase: The upper output Vi-1 is sampled by capacitors C1 and C2, and Vi-1 passes through two comparators to generate the output code qi (qi=-1, 0, or 1) of this stage. The digital output result CR of the entire pipeline can be deduced as follows:



(2) Amplification phase: Capacitor C1 is connected to the amplifier output to form a feedback loop, and capacitor C2 is connected to the voltage qiVref determined by the output code of this stage. At this time, the output generated by the amplifier is:



Under ideal conditions, the capacitors can be well matched, that is, capacitor C1=C2. At this time, the ideal transfer characteristic curve is shown in Figure 2. At the same time, the residual output Vi of this stage is:



From the comparison of equations (2) and (3), it can be seen that capacitor mismatch will cause errors in the residual output, thereby affecting the accuracy of the ADC.

3 Introduction to capacitor error averaging technology

Capacitor error averaging technology is an important calibration method that is insensitive to temperature and aging. The basic idea is to use capacitor exchange to obtain two outputs with complementary errors, and then average them to change the original error from the first order to the high order, so as to obtain a more accurate output.

3.1 Active capacitor error averaging technology

The circuit structure of active error averaging technology (ACEA) is basically the same as that of the standard pipeline ADC, except that an error averaging amplifier is added after the redundant amplifier. At the same time, the clock is changed from 2 phases to 3 phases, namely the sampling phase, the amplification phase and the averaging phase. The working process is shown in Figure 3. Since there is a mismatch between capacitors in the actual circuit, it is assumed here that the capacitor values ​​connected to the input of the redundant amplifier and the averaging amplifier are capacitors C and C(1+α) and C1 and C1(1+β), respectively, and α and β are the mismatch coefficients of the capacitors.

In the sampling phase, the input voltage Vi-1 is sampled by capacitors C and C(1+α); then in the amplification phase, capacitor C(1+α) is connected to the voltage qiVref. At this time, there is a difference between the redundant output generated by the redundant amplifier and the actual ideal value. From formula (2), it can be seen that this output Uo1 is actually the inter-stage output without calibration. At the same time, Vo1 is cross-sampled by the following capacitors C1 and C1(1+β), and its expression is:



Finally, entering the average phase, since the connection relationship between capacitors C and C(1+α) is interchanged, and capacitor 2C1 is connected to the output of the average amplifier to form a feedback loop, the redundant output generated by the redundant amplifier and the output of the final average amplifier are:



From the above analysis, it can be seen that the error of the final output expression (6) is changed from first order to second order compared with the output without calibration. Assuming the mismatch coefficient β is 3%, it can be seen that the error after calibration is reduced to 3% before calibration, thereby achieving the purpose of calibration.

3.2 Passive capacitor error averaging technology

Although the ACEA technology can get the correct output, it is at the cost of doubling the complexity of the circuit. Therefore, Chiu proposed a passive capacitor error averaging technology, referred to as PCEA technology. He used double sampling to replace the error averaging circuit in the ACEA technology, which greatly reduced the circuit scale.

Figure 4 is a schematic diagram of this PCEA technology. The basic structure of the circuit is exactly the same as that without calibration, but each conversion cycle consists of 2 sampling phases and 2 transfer phases. The inputs Vin1 and Vin2 in the figure are the two error complementary outputs of the transfer phase of the previous stage circuit. If it is the first stage circuit, the input Vin1=Vin2 is the output of the sampling and holding circuit.

For the convenience of explanation, it is assumed that Vin1=Vin2=Vi-1. Analysis shows that the two output voltages Vo1 and Vo2 of the i-th stage in transfer phase 1 and transfer phase 2 are the same as Vo1 and Vo2 in the active capacitor error averaging principle analysis, which are respectively formula (4) and formula (5). Obviously, the errors of Vo1 and Vo2 are complementary. Because Vo1 and Vo2 are sampled by the capacitors C1 and C1(1+β) of the next stage respectively, the equivalent output residual voltage on C1 and C1(1+β) after charge sharing is:



It can be clearly seen that the error voltage changes from the first order in equations (4) and (5) to the second order in equation (7), thereby achieving the purpose of capacitor error averaging. Compared with active technology, passive technology reduces the scale of the circuit by nearly half, so it can achieve the purpose of reducing power consumption, area and noise. However, since one conversion cycle requires 4 clock phases, the analog/digital conversion speed is twice as slow as that of uncalibrated, so it is suitable for occasions where speed requirements are not high but power consumption and resolution requirements are high. It is worth mentioning that due to the low performance of PCEA technology in terms of speed, references [5, 6] proposed an improved PCEA technology, which has improved the performance in terms of speed to a certain extent.

3.3 Digital capacitor error averaging technology

Since both ACEA technology and PCEA technology need to add additional clock phases when working, which reduces the conversion speed, O.Bernal et al. proposed a digital capacitor error averaging (DCEA) technology. This technology adopts the idea of ​​the above-mentioned analog capacitor error averaging technology and implements it in the digital domain. He uses the principle of capacitor error averaging to obtain the calibration coefficient, and in the calibration process, these constants are called according to the output of each level. Because DCEA technology does not need to add additional clock phases, its speed can reach twice that of PCEA technology (as shown in Table 1). The following is the working principle of DCEA technology.

According to formula (2), let C1=C(1+α), C2=C(1-αi). For the convenience of algorithm explanation, the capacitor mismatch coefficient here is defined as 2αi. It can be concluded that:

The calibration process of DCEA technology is similar to the table lookup calibration method in the literature, starting from the lowest bit and ending at the highest bit. He successfully transferred the contradiction in the analog domain of CEA technology to the digital domain. And through effective digital operations, it is solved, so that the performance of the circuit is improved.

4 Summary and Outlook

This article mainly introduces the application of three different capacitor error averaging technologies in pipeline ADC. Among them, ACEA is a typical analog calibration technology, which requires additional analog circuits and additional clocks to implement; although PCEA does not need to add additional analog circuits, it requires more clocks to process than ACEA, so it is essentially in the category of analog domain; and DCEA technology belongs to the digital calibration method. From the development of ACEA technology to DCEA technology, the calibration method has also transitioned from analog calibration to digital calibration, and the improvement of circuit performance is obvious. With the continuous improvement of people's requirements for the accuracy and speed of pipeline ADC, the research on its error calibration technology is also changing with each passing day. Since digital calibration can relatively bring lower power consumption, smaller area and greater design flexibility, it can provide a broader space for the development of calibration technology. In short, with the application of new calibration technology and the development of integrated circuit technology, pipeline ADC will continue to improve in the direction of low power consumption, high speed and high precision.