Design of 2×8 Low-Noise InGaAs/InP APD Readout Circuit

0 Introduction

In the 1310-1550 nm band of infrared communication, the main high-sensitivity detection materials are Ge-APD and InGaAs/InP APD. Compared with the two, InGaAs/InP APD has higher quantum efficiency and lower dark current noise. In0.53Ga0.47As/InP APD adopts a structure that sequentially matches the epitaxial InP buffer layer, InGaAs absorption layer, InGaAsP bandgap gradient layer, InP charge layer and InP top layer on the n+-InP substrate.

The biggest disadvantage of APD detectors is that the dark current is larger than the signal gain, so the key to designing APD readout circuits is to amplify the output weak current signal, limit the noise signal, and improve the signal-to-noise ratio. CTIA is selected as the readout unit. CTIA is an op amp integration mode that uses an operational amplifier as an integrator. Compared with other readout circuits, it has the advantages of low noise, good linearity, and a large dynamic range.

1 Working Timing and Readout Circuit Structure

As the basis of large array area array, a 2×8 readout circuit was first developed. Figure 1 shows the working sequence of the circuit, where Rl and R2 are row selection signals; Vr is the reset signal; SHl and SH2 are double sampling signals; C1, C2, ..., C8 are column readout signals. The circuit adopts a row-sharing working mode. When R1 is selected (high level), the first row is integrated. When SH1 is high level, the circuit performs sampling before integration. When SH2 is high level, sampling is performed before the end of integration. C1, C2, ..., C8 are high level in turn, and the signal on each pixel on the row is output; then R2 is high level, and the above steps are repeated to perform integration and readout of the second row.

Figure 2 is a block diagram of the 2×8 readout circuit. The chip is mainly composed of row and column shift registers, CTIA and CDS units, which are represented by dotted boxes in the figure: the shift register unit completes the row and column selection, the CTIA functional block integrates the detector current signal by row, and the CDS functional block can suppress the circuit noise, such as KTC (reset noise), FPN (fixed pattern noise), etc.; FPGA mainly generates reset signal (Vr) and sampling signal (SH1, SH2) to trigger the reset and sampling actions of the circuit. C8 is the trigger signal of this group of signals to solve the synchronization problem with the row and column selection signals in the chip.

In order to facilitate the connection simulation with the readout circuit, the circuit model of the device is first established according to the device characteristics, as shown in the dotted box in Figure 3(a), where Idet, Rdet, and Cdet represent the photocurrent, impedance, and parasitic capacitance of the device, respectively. Figure 3(a) also shows the circuit structure of the CTIA readout unit, which is mainly composed of a reset switch KR, an integral capacitor Cint, and a low-noise op amp A. In the CTIA structure, designing an op amp with high gain, low noise, small input offset, and large slew rate is the key to ensuring a high signal-to-noise ratio and a large dynamic range of the readout circuit. In addition, the design of the integral capacitor Cint is also very important. During the design process, it was found that choosing a suitable integral capacitor is also one of the keys. Figure 3(b) is a CDS unit, which consists of a differentiator composed of sampling tubes M1, M2, sampling and holding capacitors C1, C2, and M3~M6. Vin is the CDS input potential, which is also the output potential of the CTIA. Vout1 and Vout2 are two sampled outputs, which can be noise suppressed after passing through a subtractor.

2 Integral capacitor Cint

The design of the integral capacitor is mainly related to the magnitude of the detector signal current. Figure 4 shows the characteristics of In0.53Ga0.47As/InP APD. The simulation results show that the operating current of the device is generally around 300 nA.

Figure 5 shows the simulation results of the output voltage Vout when the device current is 300 nA and the integral capacitance is 2, 4, 6 and 15 pF respectively. Simulation parameter design: When the device thickness is 20 μm, the device impedance is calculated according to the device simulation results, and the device parasitic capacitance is 80 pF. The reference voltage Vb is 2.0V, and the integration time is 60μs. It can be seen that the time for the integral voltage to reach saturation is different for different integral capacitances, that is, the optimal integration time is different for different integral capacitances. If a 4 pF integral capacitance is selected, the integration time is best controlled below 40μs.

The integrating capacitor also determines the charge capacity. The charge capacity is

Where: Qm is the charge capacity; Vref is the reference voltage, generally 1.5~3 V. Formula (1) shows that increasing the integral capacitor Cint can increase the charge capacity.

In the CTIA circuit structure, KTC noise is the main noise, and KTC noise is also related to the integral capacitor. The KTC reset noise voltage can be expressed as

Where: VN is the KTC noise voltage caused by the reset on the integral capacitor; K is the Boltzmann constant, which is 1.38×10-23J/K; T is the absolute temperature, which is 77 K. Converting this noise voltage into the number of noise electrons at the input end is expressed as

Where: Nin is the number of noise electrons converted to the input end by the reset noise of the integrating capacitor KTC; q is the charge constant, whose value is 1.60×10-19C; G is the output stage gain.

Figure 6 shows the relationship between the number of noise electrons and temperature and the integral capacitor Cint. As can be seen from Figure 6, Nin decreases as the temperature decreases and increases as Cint increases. Therefore, when designing Cint, the detector current, integration time, charge capacity Qm and KTC noise converted to the number of electrons Nin at the input end must be taken into account, and a suitable value is designed in combination with the circuit operating temperature. In the readout circuit, when the operating temperature of the capacitor is 77 K and Cint is designed to be 4 pF, the reference voltage is 2 V and the charge capacity is 8×10-12J. The output stage gain of the circuit is 0.65, and the number of noise electrons converted to the input end by KTC reset noise is 768, which is less than the number of noise electrons of the actual detector, and the charge capacity is large enough to meet the needs of detector readout. In the CTIA structure, a high-gain and low-noise operational amplifier is designed. Design appropriately according to the specific application. The switch tube KR adopts a four-tube clasped tube structure to reduce the influence of the on-resistance on the circuit. Figure 7 is a photo of the readout circuit chip.

3 Conclusion

The circuit is fabricated using 0.6μm CMOS process and packaged in a 40-pin tube shell, of which 32 are effective pins. The performance of the chip is tested by electric injection method (constant current source analog device), and the current signal is 100-600 nA. The power dissipation is less than 200μW. When the integration capacitor is 4 pF, the integration time is 36μs. When the clock frequency is 0.5MHz, the total time for integration and readout of a frame of pixels is 108μs. The circuit has a charge storage capacity of 5×107, a dynamic range of about 1 V, and an output noise of 5.2×10-5Vrms. The test results show that the circuit meets the expected design requirements.