Analysis and Design of a New 0.5um CMOS Current Feedback Amplifier

1 Introduction

With the widespread application of MOS devices, the current feedback operational amplifier (CFOA) based on the CMOS circuit structure is widely used in high-frequency and high-speed electronic systems such as high-speed A/D and D/A converters, high-speed data acquisition, sensors, power supplies, video, and radio frequency because of its theoretically unlimited conversion rate and gain-independent bandwidth when working in a closed loop. CFOA has many advantages over traditional VFOA. The most important feature is that the input stage of CFOA abandons the differential circuit and adopts a complementary follower circuit to improve the input stage conversion rate; at the same time, its closed-loop bandwidth is independent of gain and there is no gain-bandwidth product limitation. However, most of the power supply voltage is greater than ±1.5V, and the power consumption is relatively large. However, this situation will be solved as the CMOS process matures. Reducing the voltage and power consumption of the circuit as much as possible is the development trend of analog integrated circuits, which has received widespread attention internationally.

The unit gain bandwidth of the circuit in the literature is relatively low, and because the bandwidth-gain product of the voltage mode is a constant, the gain will become very low when processing high-frequency signals. In addition, the conversion rate in the literature is also very low, which is not suitable for processing high-speed signals. The circuit in the literature achieves very low power consumption, but other performances can be improved. Based on them, this paper designs a CFOA based on the improved second-generation current conveyor (Second-generation Current Conveyor, referred to as CCⅡ). After simulation, it can be seen that most of the indicators have been improved to a certain extent.

2 Amplifier Design

Figure 1 shows the circuit structure designed in this paper. M1, M2, M3, and M4 constitute the input buffer stage. Z is the high impedance output terminal. Assuming that the current I1-I2=In is generated at the inverting terminal, this current is transmitted to the Z terminal through the current mirror composed of M1-M8 and M28-M29, and then converted into voltage for the next stage of amplification. Assuming the open-loop transimpedance gain is Z ( jf ), then:

The series resistors realized by MOS tubes M15-M18 and the capacitors formed by capacitors C1 and M19 are used in the circuit to perform phase compensation and eliminate the low-frequency zero point caused by the capacitors C1 and M19. Obviously, from the reverse input end to the Z end, the physical quantity transmitted linearly in the middle is current, and the amplitude of the current change is theoretically unlimited, which is the fundamental reason why CFOA can obtain high-speed characteristics.

3 Circuit Analysis

3.1 Input Level Analysis

In the circuit of Figure 1, the input stage of the circuit is composed of M1-M8 and M28-M29. The V+ terminal is the in-phase input terminal with high input impedance. The V- terminal is the inverting input terminal with low input impedance. At the same time, the push-pull structure of M3 and M4 also forms a low output impedance, which is convenient for the signal current to flow in or out. The complementary structure of M1, M2, M3 and M4 forces V- to follow V+. The current In=I1-I2 at the inverting input terminal, where I1 and I2 are the source currents of M3 and M4 MOS tubes respectively. When the signal current at the inverting input terminal is zero, I1=I2. The M20-M27 input stage provides a bias current of 1μA. When the in-phase terminal V+ inputs a positive polarity signal, the output current at the inverting terminal is provided by M3; when the in-phase terminal V+ inputs a negative polarity signal, the input current at the inverting terminal is provided by M4 tube. The differential mode transconductance gain of the whole circuit is:

The common-mode transconductance gain is:

From formulas (2) and (3), we can get:

In the equation, gm represents the transconductance of M3, R is the source resistance of M1, and r represents the source resistance of M3.

3.2 Output stage analysis

In the level transfer stage of CFOA, M11 and M12 complete the level transfer function, and also have another function of isolating the output stage from the intermediate amplifier stage to prevent the output stage from affecting the intermediate amplifier stage. As the output stage, the CMOS complementary amplifier has a large voltage gain, but has a disadvantage that the output impedance is too large, resulting in poor load capacity. The output stage designed in this paper adopts resistor feedback to reduce the output resistance and improve its driving performance.

The voltage gain of the output stage is:

The small signal circuit of the complementary output stage after Miller equivalent is shown in Figure 2. The equivalent small signal circuit is shown in Figure 3. Assuming K = Vout13 Vout11, according to Miller's theorem, we can get:

The output impedance is obtained when the input is short-circuited, so it is obvious that the K value is infinite. From R2 = R × K/ K?1, we get R2 = R, so the output impedance R0 = rds13 // rds14 // R. It can be seen that the output resistance is greatly reduced after adding feedback, and the simulation results also prove this point.

3.3 Analysis of circuit compensation principle

Capacitor Cz and resistor Rz are connected in series to compensate the circuit. The compensation principle is shown in Figure 3. The node equations are listed and solved from the above figure. If 1 gm2 << R1, R2, the two poles are far apart, and the zero point is finally solved as:

It can be seen from (10) that when RZ = 1/gm2, the zero point is eliminated, which improves the stability of the circuit. If RZ is slightly larger than 1/gm2, the zero point moves from the right half plane of the S plane to the left half plane, which can also improve the stability of the circuit.

Since a large resistor or capacitor will occupy a large area in microelectronics technology, the resistor RZ in Figure 3 is implemented by M15-M16, and M19 plays the role of a capacitor. In static state, there is no current in M15 and M16. According to the small signal equivalent circuit, the equivalent resistance of the drain-source terminal can be obtained as RZ = 1/gm, where gm is the transconductance of M15-M16. Therefore, when the transconductance of M15-M16 is reasonably designed, it can play the role of resistor RZ. In addition, MOS tubes M17-M18 also play the same role as M15-M16, and M19 and M17-M18 compensate the circuit.

4. Principle analysis and simulation

4.1 Open-loop simulation results

In Figure 1, M9 and M10 form the second gain stage of the op amp, and its small signal gain is:

Using BSM3 0.5um CMOS process parameters under PSPICE, load capacitance CL=20pF, the differential mode open-loop gain of the circuit is 84.2dB, the unit gain bandwidth is 676MHz, and the phase margin is 60°. Obviously, the circuit meets the stability requirements. The unit gain bandwidths in the literature are 1MHZ and 2.2MHZ respectively, and the unit gain bandwidth of CFOA in the literature is 79.5MHZ. It can be seen that the unit gain bandwidth of the circuit has been greatly improved.

4.2 Closed-loop characteristic analysis and simulation

The AC small signal equivalent circuit of the CFOA circuit designed in this paper is shown in Figure 4. The first stage is the input stage, using CCⅡ-. The second stage uses a traditional two-stage operational amplifier.

Analyze the small signal equivalent circuit of Figure 4, CT and RZ are internal capacitors and resistors; RF is the feedback resistor. Then: the approximate function of the closed-loop voltage gain is:

The closed-loop -3dB bandwidth is:

Equations (9) and (10) show that for CFOA, its closed-loop bandwidth can be adjusted by the feedback resistor Rf, and the closed-loop gain can be controlled by R1, thus achieving independent control of gain and bandwidth.

Using PSPICE to analyze its reverse closed-loop characteristics, when Rf = 100K is fixed and R1 is 1K, 10K, and 100K respectively, the reverse closed-loop gain is 40dB, 20dB, and 0dB respectively, and the in-phase closed-loop gain is similar. This shows that the circuit design is reasonable and reflects that the bandwidth of the CFOA gain setting is not very important.

5 Conclusion

The low-voltage and low-power CFOA in this paper only consumes 0.7mW of power, has an open-loop gain of 84.2dB, a phase margin of 62°, a common-mode rejection ratio of up to 138dB, and an output voltage range of -0.85V to 0.97V when only 1V of power supply voltage is required. Since the power supply voltage is only 1V, the power consumption is relatively small, which is extremely beneficial for portable devices and occasions that require a smaller voltage. The author's innovation in this paper is to use MOS tubes to realize series resistance to eliminate the low-frequency zero point caused by the compensation capacitor, increase the gain of the circuit through a high output impedance mirror current mirror, and use a common source and common gate current source to provide bias current for the circuit to reduce the influence of power supply voltage changes on the bias current. The parameters of this paper and the comparison with the literature are shown in the following table.