Design and application of an embedded high-performance comparator

1 Introduction

According to the general principle, the comparator compares the input signal to obtain a digital signal that can be recognized by the digital logic part [1]. It is the core unit of the A/D converter, and its accuracy, speed and other indicators directly affect the performance of the entire A/D converter. The comparator cascade structure is usually used in the converter. This structure can improve the speed, ensure the resolution, reduce the delay and power consumption, and it also has a great impact on the input voltage range, input resistance and circuit area. In addition, due to the existence of factors that affect the accuracy such as device mismatch and limited voltage range, the introduction of offset calibration technology is an indispensable step [2-8].

For a 1MS/s, 10-bit successive approximation A/D converter, the accuracy requirement of its comparator should be at least 1/2LSB, that is, 0.5mV, and the conversion rate should be above 10MHz [2]. Taking into account the design margin, the comparator discussed in this article can distinguish 0.2mV voltage, the speed can reach 20MHz, and the power consumption is only 8μW. Its advantage in meeting the performance requirements of high accuracy, medium speed, and low power consumption of embedded A/D converters is obvious. In this article, we first introduce the basic structure of the comparator, then analyze the specific circuits of each level of the comparator, and finally give the result analysis.

2 Circuit Structure Analysis

The cascaded comparator amplifies the input signal step by step to a level that can be recognized by the digital circuit. This can avoid the unstable operation caused by the excessive gain of the comparator. However, for a successive approximation A/D converter, in order to ensure a certain speed, the number of comparator cascades m must also comply with certain rules.

Using the formula m ≈ ln(1/r), we finally get m=6, where r is the resolution, which is 1/1024 here [3]. The recovery time of the comparator is a major factor that restricts the response speed. In this design, the recovery time of the single-stage comparator is 15ns, while the recovery time after cascading is 1ns. The recovery time is significantly shortened and is much less than half of the clock cycle, ensuring the reliable operation of the comparator.

The comparator designed in this paper has a differential amplifier with positive feedback in the first three stages, which can quickly build up the input signal to an amplitude that can be processed by the digital circuit. It has a simple structure and is a good choice for medium and high speed comparators [4]. In comparison, the last three stages of the circuit are simple inverters.

On the other hand, in order to achieve 10-bit resolution, capacitor coupling is used between comparators to eliminate the offset voltage by superimposing the offset voltage stored on the capacitor with the input. This design adopts a hybrid offset calibration technology, that is, it uses both input offset calibration (IOS) and output offset calibration (OOS) technology. IOS stores the offset voltage in the input coupling capacitor by forming a unity gain, while OOS stores the offset voltage in the output coupling capacitor by shorting the input. For the same preamplifier, the OOS method can obtain a smaller residual offset voltage, and the coupling capacitance in OOS is smaller than that in IOS. However, the OOS method usually has a strict control on the gain of the preamplifier, while the feedback structure formed in the IOS method can force the preamplifier into the working area. Therefore, people usually use a multi-stage structure of the two methods [5].

2.1 First-stage comparator structure

In order to reduce the comparator's small signal output settling time, the general rule is to require the first-stage comparator to have a certain gain and a sufficiently large bandwidth [3]. The positive feedback of the gate crossover can greatly increase the circuit gain, but in order to better achieve the indicators, this design uses a comparator composed of two-stage op amps.

The structure is shown in Figure 1. M1 and M2 form an input-output differential pair, and M5, M7, M6, and M8 form a gate-crossed load with positive feedback. This state can improve the gain of the circuit, and the transconductance of M5 and M6 is smaller than that of M7 and M8, making this circuit a weak feedback. As for M3 and M4, they form the second-level positive feedback [6]. By optimizing the width-to-length ratio of M3 to M8 in the positive feedback, the purpose of reducing static current and corresponding power consumption can also be achieved.

By performing AC simulation on it, it is found that the gain of the first stage is 20dB and the bandwidth is 62.5MHz. The performance is obviously better than that of the first-stage op amp, which verifies the correctness of the choice.

In addition, the first-stage comparator only uses the output offset calibration technology (OOS), and the offset voltage is stored on the capacitor after amplification. In this case, it is easy for the coupling capacitor to saturate. In order to prevent this result, the designer must strictly control the gain of the first stage [5]. As shown in the figure, this stage of the comparator is implemented by two stages of op amps. Then first calculate the DC voltage gain of the first stage. Assume

Figure 3 shows its simulation waveform. The two inputs have their own values ​​when the clock is at a low level, and they are equal when the clock is converted to a high level.

2.2 Structure of the Second-Stage Comparator

Comparator 2 is basically the same as comparator 1, except that a switch is added between the input and output of the first-stage op amp. When the control clock is low, the comparator output is connected to the opposite input terminal for offset calibration. Assuming that the charge mismatch injected into the capacitor by switches S1 and S2 is △Q, C1=C2=C, then the remaining input offset / OS V ∝ ΔQ C It can be seen that increasing C can reduce the remaining offset voltage, but increasing C will extend the reset and output setup time, and increase the area, so we compromise and select C=544.5fF[5]. The gain of this amplifier is 13.

2.3 Structure of the third-stage comparator

This comparator is still composed of two stages of op amps. The first stage op amp improves the gain of the original circuit by adopting a weak positive feedback structure with gate crossover and optimizing the width-to-length ratio of the tube, but at the cost of reducing the bandwidth. The gain of this stage of amplifier is 730. The second stage op amp uses a mirror circuit to form a single-ended output.

3 Results Analysis

3.1 Overall simulation

The comparator discussed in this article uses the SIMC 0.25μm CMOS process model, selects the power supply voltage as 2.5V, the clock cycle as 250ns, and uses Hspice for transient simulation. Set Vref=1.25V, Vin changes every 50ns, and is 1.2498V, 1.2502V, 1.25V, 1.2502V, 1.2498V respectively. When the clock is high from 0 to 50ns, the comparator is in the offset calibration stage. Simulation Figure 4:

3.2 Power consumption analysis

The transient current value of the entire comparator is shown in Figure 5. It can be seen from the figure that when the clock signal jumps, it will give a large impact to the transient current, so reducing the clock conversion rate can reduce power consumption. At the same time, power consumption is the product of voltage and current, and reducing the power supply voltage can also achieve the purpose of reducing power consumption. Taking all factors into consideration, this design uses a clock signal with a duty cycle of 1/5, a period of 250ns, and a power supply voltage of 2.5V. In addition, this design has a simple structure and reduces the number of effective MOS tubes, which is another major factor in reducing power consumption. By using Cadence's calculation tool, the average current is 3.23μA and the power consumption is 8μW.

4 Conclusion

The innovation of the author of this paper is to cascade six-stage comparators, of which the first three stages are two-stage operational amplifiers with gate cross positive feedback, which can quickly amplify the signal and shorten the settling time; the whole circuit structure is simple and occupies a small area; after comprehensive consideration, this design uses a clock signal with a period of 250ns and a power supply voltage of 2.5V to greatly reduce power consumption; it introduces input offset calibration (IOS) and output offset calibration (OOS) mixed calibration technology and self-clearing technology to improve the accuracy of the comparator. This comparator meets the performance requirements of high precision, medium speed and low power consumption of embedded 10-bit successive approximation A/D converter.