Design of 2.5Gb/s transceiver multiplexer circuit using 0.18um CMOS

1 Introduction

In recent years, with the rapid development of traditional telecommunications services and Internet services, they have put forward higher and higher requirements for network bandwidth, which has led to the emergence of high-speed serial interfaces. At present, the research and development of 2.5 Gb/s ultra-high-speed serial transceiver CMOS chips and IP cores in China is still in its infancy. Designing and developing high-performance serial transceiver chips and IP cores with independent intellectual property rights can break the monopoly of foreign countries on high-end router and switch chips, which can not only directly and significantly reduce the cost of communication and network equipment, generate significant economic benefits, but also bring huge social benefits. The multiplexer designed in this paper is used in a 2.5Gb/s transceiver system. The system block diagram of the transceiver is shown in Figure 1.

Figure 1 Transceiver structure diagram

It is well known that in high-speed data transmission systems, transceivers play a vital role in realizing the functions of the entire system. In transceiver systems, multiplexers are one of the circuit units that work at the highest speed, so the quality of multiplexer circuit design directly affects the performance of the entire system. The multiplexer designed in this paper is implemented using SMIC 0.18µm CMOS process.

2 Circuit structure and design

2.1 16:1 multiplexer structure design

The 16:1 multiplexer designed in this paper converts the 16-bit 156.25Mb/s parallel data output by the transmission data selection module into 2.5Gb/s serial data output. Its implementation block diagram is shown in Figure 2. The circuit is mainly composed of a 16:4 multiplexer circuit and a 4:1 multiplexer circuit implemented in a tree structure (including 3 2:1 multiplexers). The 16:4 multiplexer is implemented with a digital circuit, and the 4:1 multiplexer circuit is implemented with an analog circuit. The circuit receives 2.5GHz, 1.25GHz and 625MHz differential clocks sent from the PLL, and provides the required clocks for the 16:4 multiplexer and 2:1 multiplexer circuits. After the 16-bit parallel input data passes through the 16:4 multiplexer, the 4-bit parallel data is output and sent to the 4:1 multiplexer. After the 4:1 multiplexer, the data is converted into a 1-bit wide serial data stream, and the sending order is the lowest bit first, that is, TXD_P[0] appears first on TXD_S, and TXD_P[15] is sent last. Since this circuit is a mixed signal design, it is necessary to add excitation to the digital circuit and the analog circuit separately during simulation. For the 4:1 multiplexer circuit, the input uses a complementary square wave voltage source with a peak-to-peak value of 0.4V. For the 16:4 multiplexer circuit, the excitation is added by describing it in the Verilog language. Since the two modules are implemented by digital circuits and analog circuits respectively, level conversion must be performed at the connection between the two modules. In Virtuoso AMS Simulator, the interface model is divided into two types: A2D type and D2A type. This design is to send signals from digital circuit to analog circuit, so the D2A interface model is used. The model has four main parameters: d2a_tf, d2a_tr, d2a_vh and d2a_vl. Among them, d2a_tf and d2a_tr represent the time required for the output of the interface model to rise from the current value to d2a_vh and fall to d2a_vl respectively; d2a_vh and d2a_vl represent the final voltage value converted from the logic "1" and "0" in the corresponding digital circuit respectively. The settings of this design are as follows: d2a_tf=20ps, d2a_tr=20ps, d2a_vh=1.8V, d2a_vl=1.4V.

Figure 2 16:1 multiplexer implementation block diagram

2.2 Unit Circuit Design

2.2.1 16:4 Multiplexer Circuit

The 16:4 multiplexer circuit consists of four 4:1 multiplexer modules and one assignment statement module. This circuit is described in Verilog language. The function of the four 4:1 multiplexers is to multiplex 16 channels of 156.25M data TXD_P[15:0] into four channels of 625M data. Here we use a shift register to implement a 4:1 multiplexer. First, the 16-bit parallel data is divided into four 4-bit parallel data, and then the 4-bit parallel data is sent to the 4:1 multiplexer. The output of the data after passing through the 4-bit shift register is shown in Figure 3. Since the analog circuit of the subsequent stage requires differential input, the output of this module is complementary output.

Figure 3 16:4 multiplexer implementation timing diagram

The key code of the Verilog implementation of the 4:1 multiplexer circuit is as follows:

2.2.2 4:1 Multiplexer Circuit

The 4:1 multiplexer is implemented in a tree structure, as shown in Figure 2. It is mainly composed of three 2:1 high-speed multiplexers and a master-slave D flip-flop (MSDEF). The 2:1 multiplexer consists of a master-slave D flip-flop (composed of two latches in cascade), a master-slave master D flip-flop (composed of three latches in cascade), and a 2:1 data selector.

The latch and 2:1 data selector designed in this paper are both implemented using CML (current mode logic) logic. Its basic structure is shown in Figure 4(a). According to its function, it can be divided into three parts: pull-down logic network, tail current source and pull-up resistor. It can work normally under small voltage swing. Due to the existence of tail current source, the power consumption of CML circuit is approximately a constant value P=vdd*I, where vdd is the power supply voltage and I is the DC tail current. It is well known that the power consumption of traditional CMOS circuit is P=CL`*f*vdd2, where f is the switching frequency of the circuit and CL` is the load capacitance of the output node. Therefore, under high-speed conditions, the power consumption of CML circuit is much smaller than that of similar CMOS circuits. In addition, reducing the voltage swing of CML circuit can also reduce the delay of the entire circuit, thereby improving the working speed of the circuit.

Figure 4 Latch and 2:1 data selector circuit diagram

3 Simulation Results

The circuit is simulated using the SMIC 0.18µm process model and the Virtuoso AMS Simulator tool. The input signal is 16-bit 156.25Mb/s parallel data, as shown in Figure 5(a). The simulated corners include: ff (fast model), tt (typical model), and ss (slow model). The simulated output waveforms under different corners are shown in Figure 5(b)-(d). From the simulation results, it can be seen that when the input data is 156.25Mb/s, the multiplexing function can be well realized, the output data rate is 2.5Gb/s, and the power consumption of the entire circuit is about 6mW.

Figure 5 Simulation waveforms under different corners

4 Conclusion

With the development of CMOS technology, high-performance, low-power, and low-cost high-speed circuits can be designed using CMOS technology. This design uses 0.18µm CMOS technology, CML circuit design technology, and digital-analog hybrid design technology to design a 2.5Gb/s 16:1 multiplexer circuit. The circuit can work at a rate of 2.5Gb/s with a power supply voltage of 1.8V and an operating temperature range of 0-70°C, and the power consumption is about 6mW.

The author's innovative viewpoint: This paper modularizes the 16:1 multiplexer circuit, uses the mixed-signal design technology to design the 16:4 multiplexer circuit and the 4:1 multiplexer circuit using the Verilog language description and CML circuit logic, and verifies the designed 16:1 multiplexer using the mixed-signal simulation verification method. This method greatly shortens the time required for design and verification.