Principle and Application of Dual Sigma-Delta Converter with Auxiliary DAC

1. Internal block diagram

This dual Σ-Δ analog-to-digital converter with auxiliary DAC recently launched by AD is a complete 15-bit CMOS analog-to-digital converter. It has high sampling rate, low power consumption, and the input end has signal processing function. The two Σ-Δ ADCs with digital filters on the receiving channel share a bandgap reference. The control DAC can perform the AFC function, and other auxiliary functions can be obtained from the auxiliary serial port to meet the performance requirements of the device in many aspects.

Figure 1 shows the internal block diagram of the AD7729. The AD7729 consists of two main parts: the analog-to-digital converter and the auxiliary digital-to-analog converter. The analog-to-digital converter consists of a Σ-Δ ADC, a digital filter, an offset adjustment, and a main serial communication interface; the digital-to-analog converter consists of a 10-bit auxiliary DAC, an output buffer, and an auxiliary serial interface.

1.1 Analog-to-Digital Converter

The analog-to-digital converter section has two channels, I and Q, each consisting of a switched capacitor filter and a 15-bit ADC. The on-chip digital filters play a key role in the performance of the system, and their amplitude-frequency and phase-frequency response characteristics ensure excellent suppression of mutual interference between adjacent channels.

a. Σ-Δ ADC

The switched capacitor filter samples the received analog quantity at a rate of 13MHz, and its frequency response is shown in Figure 2(a). The clock frequency of another digital filter on the receiving channel is 6.5MHz, and its frequency response characteristics are shown in Figure 2(b). The corresponding integrated frequency response of the two filters is shown in Figure 2(c). The receiving channel of AD7729 adopts Σ-Δ conversion technology to implement system filtering on the chip, thereby ensuring 15-bit high-precision output at the I and Q ends. The specific working process is to use a charge-balanced modulator to sample the output of the switched capacitor filter at a rate of 6.5MHz and convert it into a digital pulse train. The excessive oversampling rate can disperse the quantization noise of 0?.25MHz and reduce it in the frequency band of interest. Then a high-order modulator is used to shape the noise spectrum. The digital filter is then used to process the out-of-band noise and simultaneously convert the digital pulse into parallel 15-bit binary data.

b. Digital filter

It has 288 taps and a settling time of 44.7μs. We have introduced its two important functions: system filtering and out-of-band quantization noise elimination. It can be seen that it has two advantages over analog filters: first, because it is located after the ADC, it eliminates the noise generated during the A/D conversion process; second, it not only eliminates the low-pass ringing, but also ensures a linear phase response. Although these functions are difficult to achieve with analog filters, analog filters eliminate the noise carried by the signal before A/D conversion. Because the peak of the noise has the danger of saturating the analog modem, AD7729 specifically sets an over-range margin for the modulator and filter, allowing 100mV of over-range drift.

1.2 Digital-to-Analog Converter

a. Auxiliary control function

This function is implemented by the auxiliary DAC. It consists of several high impedance current sources, followed by a very light load to ensure its DC accuracy. The auxiliary DAC has an output amplifier that allows a load resistance of 10kΩ. The analog output of the DAC is 2VREFCAP/32 + (2VREFCAP-2VREFCAP/32) × DAC/1023. Among them: VREFCAP is the reference voltage. DAC is the digital signal to be output.

b. Reference voltage and serial port

REFCAP is a bandgap reference that is low noise and provides temperature compensation for the ADC and auxiliary DAC. The reference voltage VREFCAP = 1.3V. Both the main serial interface (BSPORT) and the auxiliary serial interface (ASPORT) are DSP (digital signal processor) compatible serial ports. Users can freely choose how to connect registers to ports, and can also reduce power consumption by adjusting the frequency of SCLK.

c. Read/write operations

The read and write operations of the registers through the serial port are to convert the 16-bit word length data, that is, 10 data bits and 6 address bits (except Rx). A certain address must be given to the read-only register to read the corresponding content from it. The time interval between writing and reading is about 4 main clock cycles.

2. Pins

The AD7729 is available in 28-pin TSSOP and 28-pin SOIC packages. The pinouts are listed in Table 1.

3. Circuit adjustment

3.1 Calibration

The digital filter itself is a calibration method. Generally speaking, there is an offset register on each channel of the digital low-pass filter. The value of the DC offset in the analog circuit is stored in it. Generally, the filter has cleared the offset information of the register before the data enters the serial output pin. Therefore, self-calibration or user calibration can be selected to remove the deviation in the I and Q channels. The difference is that self-calibration can only eliminate internal deviations, while user calibration can calibrate external deviations by writing information to the offset register. The offset register can accommodate a maximum of 162.5mV of DC offset, and input beyond the range will result in erroneous output. However, when a signal with an offset of more than 100mV enters, the Σ-Δ modulator automatically shifts gears. The corresponding relationship between the value of the complement in the offset register and Rx is shown in Figure 3.

AD7729 has a complete self-calibration procedure: when Rx is set, the stabilization of the analog circuit and the digital circuit requires time TSETTLE. Calibration is only started when the RxAUTOCAL bit of the main control register A (BCRA) is at a high level. In the internal self-calibration mode, the AD7729 uses a short-circuited differential input to measure the offset value in the ADC; in the external self-calibration mode, the AD7729 maintains the normal connection of the input to allow the existence of system bias. RxDELAY1 and RxDDELAY2 are the timing times of the two timers respectively. When RxDELAY2 expires, 15 bits of invalid data will be output.

3.2 Rx receiving process

When Rx is set, the SDO pin of the serial port will output Rx data at a rate of 270k words. The output result of AD7729 is 16 bits, that is, the data bits in the form of binary complement and a sign bit (LSB), which is used to distinguish I and Q. When LSB=0, the output is I, otherwise it is Q. As long as RxON is at a high level, the frequency of the serial clock remains at 13MHz, regardless of the value in the clock rate register. When the SDO pin automatically outputs Rx data, a frame synchronization signal is generated at the same time, with an interval of 48 main clock cycles. Both the auxiliary serial port ASPORT and the main serial port BSPORT can output data, but the user can only select one according to the need, and data cannot be exchanged between the two ports at the same time.

3.3 Power off

Each part of the AD7729 can be powered off. The Rx analog-to-digital converter and the auxiliary digital-to-analog converter can be powered off by setting the appropriate bits on the control register. When each part of the AD7729 is powered on, the analog circuit and the digital circuit require a settling time, and the reference voltage VREFCAP also requires a power-on time. To reduce the time required for power-on, the ADC and DAC can be put in power-off mode by setting LP to 1, while the REFCAP pin will remain in power-on mode, without the need for power-on and settling time, thereby reducing the time required for stable operation after power-on. The ADC and DAC can be powered off separately through the appropriate control register. When all components including the reference are in the power-off state, the main clock also stops working after a delay of 64 clock cycles.

3.4 Reset

Pin RESETB can reset all control registers. The reset value of ASCLKRATE and BSCLKRATE is 4 to ensure that the frequency of ASCLK and BSCLK signals is one eighth of MCLK. The other control registers are reset to 0. At the same time, these registers can also be reset by the RESET bit on the main register and auxiliary register. All auxiliary registers are reset by giving a high level to the ARETSET position on the control register ACRB, while the main register is reset by giving a high level to the BRETSET position on the control register BCRB. The required time is 4 main clock cycles. After reset, the reset value of ARESET and BRESET is 0. Registers ARDADDR, BRDADDR, ASCLKRATE, and BSCLKRATE can only be reset by reset pin RESETB, which requires 8 main clock cycles. The functions of the control registers are listed in Table 2.

4. Interface Examples

AD7729 also provides users with a standard serial port compatible with DSP, with the serial clock of the ADC controlling the serial data and I/O DSP information.

Figure 4 is the interface schematic diagram of AD7729 and ADI's ADSP-21xx. For ADSP-21xx, the serial port control register must be set to TFSR=RFSR=1 (to ensure frame synchronization of each converter), SLEN=15 (16-bit word length), TFSW=RFSW=0 (normal frame synchronization), INVIFS=INVRFS=0 (high-effective frame synchronization signal), IRFS=0 (external RFS), ITFS=1 (internal TFS) and ISCLK=0 (external serial clock).

AD7729 is a dual Σ-Δ analog-to-digital converter with auxiliary DAC. It not only has the advantages of low noise, high precision, and fast working speed, but also can be interfaced with a variety of DSPs, and has strong versatility. Therefore, this device is a new generation of ideal data acquisition and analog-to-digital conversion devices, which can be widely used in communications, multimedia and high-performance instruments.