Application of CPLD in signal filtering and anti-interference

    Abstract: Filtering and anti-interference are issues that must be considered in any intelligent instrument system. In traditional application systems, the filtering part often takes up more software and hardware resources. The emergence of complex programmable logic devices (CPLD) has opened up a new way to solve this problem. Using CPLD to implement filtering is an efficient and reliable method. This paper introduces the use of MAX+PLUS Ⅱ to program CPLD to filter and resist interference of sensor and button signals. This approach has been used successfully in product development.

    1 Overview of filtering and anti-interference

    The input signals of microcontroller application systems often contain various noises and interferences, which come from measured signal sources, sensors, external interference sources, etc. In order to improve measurement and control accuracy, noise and interference in the signal must be eliminated. There are two major types of noise: one is periodic; the other is irregular. A typical representative of the former is 50Hz power frequency interference. Hardware filtering is generally used, and a double-integration A/D converter with an integration time equal to an integer multiple of 20ms can be used to effectively eliminate its impact on the signal. The latter is a random signal, which is not a periodic signal and can be eliminated or filtered by digital filtering methods. The so-called digital filtering is to reduce the proportion of interference signals in useful signals through certain calculation or judgment procedures, so it is actually a kind of software filtering. Hardware filtering has the advantage of high efficiency, but it requires increased system investment and equipment size. When the nature of the interference changes, we often have to reconnect the circuit; software filtering is implemented using programs and does not require additional equipment, so the investment is small. , high reliability, good stability, and can filter signals with very low frequencies. As the nature of interference changes, only the software can be modified. It has the advantages of flexibility, convenience, and powerful functions, but it requires system resources and reduces the cost. system efficiency. A traditional actual system often uses a filtering method that combines software and hardware. This combination is to find a balance between the advantages and disadvantages of the two.

    Hardware anti-interference mainly uses isolation technology, twisted pair transmission, impedance matching and other measures to suppress interference. Commonly used isolation measures include using A/D, D/A to isolate the microcontroller, and using isolation devices such as relays, photoelectric isolators, and photoelectric isolation solid-state relays (SSR) to isolate switching quantities.

2 Use CPLD to realize digital filtering and anti-interference

    The method of using CPLD to realize signal filtering and anti-interference introduced here has been verified in the development of intelligent instrument pump pulse measuring instrument. The following describes how to use CPLD to implement functions such as filtering, latching, and interrupt application for the system's four external sensor pulse signals and four key signals.

2.1 Sensor signal filtering

    Since the sensor signal needs to be digitally filtered, the CPLD needs to introduce a clock signal, so we define an input terminal clki for the CPLD as the counting pulse input terminal of the digital filter. Clki is timed to generate 500Hz pulses by the microcontroller timer 1. Taking one channel as an example, the pump signal filtering part is shown in Figure 1.

    oo0 is the signal output by the proximity switch after level conversion. When oo0 is low level, it means that pump 1 is not in action, the three-terminal AND gate is blocked, the clock signal clki cannot pass, and the counter bcn3n does not count. In the same way, when aa4 is high level, the three-terminal AND gate is also closed (the changes and functions of aa4 will be introduced below). Therefore, when oo0 is high and aa4 is low, clki turns on the counter CLK end. When either oo0 or clr is low, the counter is cleared. Counter ban3n is programmed by the text programmer of MAX+PLUS II. Its text is as follows:

    SUBDESIGN bce3n

    ( clk:INPUT;

    q[4..0]: OUTPUT;)

    VARIABLE

    count[4..0]

    BEGIN

    count[ ].clk= clk

    count[ ]=count[ ]+1

    q[ ]=count[ ]

    END

    Its output aa[4..0] is equal to the current count value of the counter. aa4 is the highest bit of aa[4..0]. When the count value reaches 10H (hexadecimal), that is, when aa4 is high level, the three-terminal AND gate is blocked and the counter remains unchanged at 10H unless there is a clear signal. . Its waveform is shown in Figure 2.

2.2 Interrupt application signal generation

    The interrupt application signal is generated by the circuit in Figure 3.

    The highest bits of the four counters in the figure are connected to the four-terminal OR gate. As long as one signal is high, the output of the OR gate is high, and after passing through the NOT gate, the output is low level, which is connected to the clock end of the D flip-flop. The D terminal of the D flip-flop is initially high. The D flip-flop is a rising edge flip-flop. If the input D is 1, at the rising edge of the clock pulse, "1" is sent to the flip-flop, so that Q = "1". Only when the clr signal at the CLRN end is valid, the D flip-flop is cleared and Q="0". The waveform is shown in Figure 4.

    If multiple pulse signals overlap, for example, two signals overlap, and the interrupt signal will only be generated when all four signals are low, so the signals need to be latched. This design uses a D flip-flop to realize the latch, and the circuit is shown in Figure 5.

    When aa4 changes from low to high, a4 becomes high level and is cleared by the clr signal.

2.3 Button debounce and data output

    button debounce is also implemented through a counter. The circuit schematic is shown in Figure 6.

    When the button is not pressed, it is high level, blocking the clock signal. When the key is pressed, the counter starts counting. When the highest bit of the counter output is "1", the clock signal is also blocked to prevent the key press time from being uncertain and the required k14 signal being fixed. When the key signal is high level, the counter is cleared to prevent the counter from accumulating interference signals and causing malfunction. The waveform is shown in Figure 7.

    The processed signals a4, b4, c4, d4, k04, k14, k24, k34 of the pump and button are hung on the data bus via 74373, as shown in Figure 8. The 74373 enable signal is generated by the circuit in Figure 9.

    It uses text editing, as follows:

    SUBDESIGN bcn5n1

    (

    a15,all,a10,a9,a8,wr,rd:INPUT;

    en373:OUTPUT;

    )

    BEGIN

    En373=!(a15&a11&!a10&!a9&!wr&!rd)

    END

    If the microcontroller If a signal is sent to read the number in address 81XXH, this 373 will be gated and the number will be read.

    The above introduces the use of CPLD to achieve digital filtering and anti-interference. This design has been successfully applied in product development with good results and achieved the expected purpose. We have mentioned before that a traditional design often finds a balance between the advantages and disadvantages of software filtering and hardware filtering. To use our usual idioms, this can be said to be to make use of strengths and avoid weaknesses or to learn from each other's strengths. We have always regarded these two idioms as complimentary, but if we take a closer look at them, it seems that they are not entirely good representatives: carrying forward strengths is certainly commendable, but avoiding weaknesses may not be the best way to solve problems. After all, Avoidance cannot solve the essence of the problem. Even if you use its strengths to make up for its shortcomings, it is not a long-term solution. It is better to directly overcome the shortcomings. Using CPLD can combine the advantages of both software and hardware filtering, while discarding their shortcomings, thereby achieving the purpose of maximizing strengths and eliminating weaknesses. Using CPLD to implement filtering only takes up less resources, so it can be used to implement other digital circuits and implement filtering at the same time.