Large signal detector circuit--series diode peak envelope detector

Large signal detector circuit--series diode peak envelope detector

Large signal (above 0.5V) detector, also called envelope detector.

1. Series diode peak envelope detector

The principle circuit of this detector is shown in Figure 5.5-10A. In the circuit, the signal source U1, the diode VD and the detection load RLCL are connected in series, so it is called a series diode peak envelope detector. The circuit works by using the unidirectional conduction of VD and the charging and discharging of the detection load RLCL. Whether VD is turned on or not depends on the difference (U1-U0) between the high-frequency input voltage U1 and the output voltage UO (that is, the voltage UCL on the capacitor CL). During the period when the high-frequency signal is positive half cycle (U1-U0)>0, VD is turned on, and the high-frequency current ID flowing through VD charges CL when it is turned on. The charging time constant is RDCL (RD is very small, which is the internal resistance when VD is turned on). It is very small, and U0 is close to the maximum value of the high-frequency voltage in a very short time. During (U1-U0)﹤0, VD is cut off, and capacitor CL discharges through RL. Since the discharge time constant RLCL (>RDCL) is much longer than the high-frequency signal period, the discharge is very slow. In this way, the charge and discharge are repeated repeatedly, and the voltage waveform shown in Figure 5.5-10B is obtained. Since the amplitudes of U0 and U1 are quite close, the peak envelope detection is named after this.

Figure 5.5-10C is the current and voltage waveform of the detector diode. ID is in pulse shape, and its amplitude changes with the change of U1 envelope. The voltage drop of the average current UDEV contained in ID on the load RL is the output voltage UO. It can be proved that when U1=UC(1+MACOSOT)COSOCT, the modulation signal component UOO in UO is:

Where θ is half of the conduction angle of the diode when it is conducting, and it is a constant related only to RD and RL. The relationship among θ, RL, and RD is:

R1D is determined by θ, that is, it depends on RD/RL. Therefore, the R1D value can also be found according to the RD/RL value through Table 5.5-3.

Envelope detectors often have two types of nonlinear distortion: one is diagonal cutting distortion, and the other is negative peak cutting distortion.

Figure 5.5-11 shows the diagonal clipping distortion. The reason for this distortion is that the time constant RLCL of the detection circuit is too large, so that the discharge rate of the capacitor CL cannot keep up with the envelope change rate. In order to avoid the generation of diagonal clipping distortion, the time constant RLCL must satisfy the following formula when selecting single-tone modulation:

The above formula shows that the larger the ohm of MA, the faster the envelope drops, and the smaller the RLCL value required to avoid diagonal clipping distortion. In multi-tone modulation, as an engineering estimate, the maximum value of ohm and MA should be taken.

Figure 5.5-12 shows the negative peak clipping distortion. It is caused by the difference between the low-frequency AC load resistance and the DC load resistance RL of the detector. The reason for the difference in AC and DC load resistance is the presence of a large DC blocking capacitor CC. Under steady-state conditions, there is a DC voltage U= (≈UC) on CC, and its voltage drop on RL is:

URL is negative for diodes. When MA is large, the negative half cycle of the input AM wave envelope may be lower than URL. During this period (F1~F2), the diode is cut off, thus generating waveform distortion as shown in Figure 5.5-12C, which cuts the negative peak of the output low-frequency voltage. To avoid such distortion, it is necessary to ensure that (UC-MAUC) URL is:

Figure 5.5-13 is a typical example of the detection stage and related additional circuits in a semiconductor radio receiver. R1, R2, and RL2 form an external forward bias circuit. A fixed forward bias current (usually around 20~50UA) is provided to the diode VD through a -6V power supply to improve the detection efficiency. R2C3 forms a low-pass filter to filter out the low-frequency AC component in the output of both ends of RL2, extract the DC component, and add it to the base of the pre-stage amplifier as an automatic gain control voltage. The output filter circuit of the detector is connected into an X-type filter circuit, which can not only further filter out the residual high-frequency components in the output voltage, but also help avoid the generation of negative peak cutting distortion.

Figure 5.5-14 is the actual circuit of the TV receiver image detector. Since the modulation signal is a 6MHZ image signal, in order to ensure that no diagonal cutting distortion is generated and to avoid frequency distortion at the high-end frequency after detection, the capacitor C1 is selected to be relatively small. Since C1 is small, it is not enough to filter out the high-frequency component by itself, so the LC2 filter is connected. The resistor R2 is connected in series with the diode to improve the detection linearity. At this time, the transmission coefficient decreases, but generally the change is not significant.