Suggestions for improving ADC performance

Although ADCs look very simple, they must be used correctly to achieve optimal performance. ADCs have the same performance limitations as simple analog amplifiers, such as limited gain, offset voltage, common-mode input voltage limitations, and harmonic distortion. The sampling nature of ADCs requires us to consider clock jitter and aliasing more. The following guidelines can help engineers get the most out of ADCs in their designs .

Analog Input

Take the analog input signal of the ADC seriously and try to keep it clean. "Useless input" usually leads to "digital useless output". The analog signal path should be kept away from any fast switching digital signal lines to prevent noise from coupling into the analog path from these digital signal lines.

Although the simplified block diagram shows single-ended analog inputs, differential analog inputs are often used on high-performance ADCs. Driving the ADC differentially provides greater common-mode noise rejection and generally achieves better ac performance due to smaller on-chip signal swings. Differential drive is typically implemented using a differential amplifier or transformer. Transformers can provide better performance than amplifiers because active amplifiers introduce additional noise sources that affect overall performance. However, if the signal being processed has a dc component, transformers with dc blocking properties cannot be used. The noise and linearity performance of the driver amplifier must be considered when designing the pre-driver circuit. It is important to note that because high-performance ADCs typically have very high input bandwidths, filtering directly at the ADC input pins can reduce the amount of broadband noise that is mixed into the baseband.

Reference input

The reference input should be treated as another analog input and must be kept as clean as possible. Any noise on the reference voltage (VREF) is indistinguishable from noise on the analog signal. The required decoupling capacitors are specified in the data sheet of the general ADC. These capacitors should be placed as close to the ADC as possible. In order to save board area, PCB designers sometimes place decoupling capacitors on the back of the PCB, which should be avoided as much as possible because the inductance of the vias will reduce the decoupling performance of the capacitors at high frequencies. VREF is usually used to set the full-scale range of the ADC, so reducing the VREF voltage value will reduce the LSB value of the ADC, making the ADC more sensitive to system noise (the LSB value of a 1V full-scale 10-bit ADC is equal to 1V/210=1mV).

Figure 1: Typical analog-to-digital converter functional block diagram

Clock Input

Depending on the application, the digital clock input may be as important as the analog input. There are two major sources of noise in ADCs: one is caused by the quantization of the input signal (proportional to the number of bits in the ADC), and the other is caused by clock jitter (sampling the input signal at the wrong time). According to the following formula, quantization noise will limit the maximum possible signal-to-noise ratio (SNR) value in non-oversampled ADC applications.

Where N is the number of bits of the ADC and SNR is the signal-to-noise ratio.

This makes intuitive sense: for every additional bit, the total number of ADC codes doubles, and the quantization uncertainty is reduced by half (6dB). Therefore, a 10-bit ADC can theoretically provide an SNR of 61.96dB. Any jitter on the sampling clock will further degrade the SNR according to the following equation:

where SNRj is the jitter-limited SNR, fa is the analog input frequency, and tj is the root mean square (rms) value of the clock jitter.

Digitizing a 70MHz analog signal with a sampling clock that has 8ps jitter gives a jitter-limited SNR of approximately 49dB, which is equivalent to reducing the performance of a 10-bit ADC to approximately 8 bits. The clock jitter must be less than 2ps to achieve an SNR equivalent to a 10-bit ADC. There are many second-order factors that affect SNR, but the above equation is a very good first-order approximation. Differential clocks are often used to reduce jitter.

Power Input

Most ADCs have separate power inputs, one for analog circuitry and one for digital circuitry. It is recommended to use sufficient decoupling capacitors as close to the ADC as possible. Minimize the number of PCB vias and the trace length from the ADC power pins to the decoupling capacitors to minimize the inductance between the ADC and the capacitors. Just like the reference voltage decoupling, board designers sometimes place the decoupling capacitors on the back of the PCB under the chip to save board area. For the same reason, this should also be avoided. The ADC data sheet generally provides recommended decoupling solutions. In order to achieve specific performance, power and ground are often implemented using dedicated PCB layers.

Digital Output

The ADC switching digital signal output will generate transient noise and couple back to the sensitive analog circuit part in the ADC, causing failure. Shortening the output trace length to reduce the capacitive load driven by the ADC can help reduce this effect. Placing a series resistor at the ADC output can also reduce the output current spike. The ADC data sheet usually has some design recommendations for this.