Design of Sample-and-Hold Circuit in 13-bit 40MS/s Pipeline ADC

This paper analyzes the structure of the sample-and-hold circuit of the pipeline ADC and its main modules such as the gain-boosting operational amplifier circuit, common-mode feedback circuit and switch circuit, and designs each module. Finally, a sample-and-hold circuit suitable for 13 bit 40 MHz pipeline ADC is designed. Simulation results show that the sample-and-hold circuit meets the design requirements.

1 Sample and hold circuit structure

The structure of the sample-and-hold circuit directly determines the accuracy and speed of the sample-and-hold circuit. Figure 1 shows two commonly used fully differential structures: charge redistribution type and capacitor flip type. The fully differential structure can effectively eliminate DC bias and even-order harmonic distortion, and suppress common-mode noise from the substrate.

Compared with the charge redistribution structure, the feedback coefficient of the capacitor flipping structure is 1, which is twice that of the charge transfer structure (when Cs=Cf=C, the feedback coefficient is 0.5). Therefore, at the same closed-loop bandwidth, the op amp unit gain bandwidth (GBW) required by the capacitor flipping structure is only half of the GBW of the capacitor charge redistribution structure, so the capacitor flipping structure has the advantage of low power consumption [3]. In addition, since the charge redistribution circuit requires four capacitors, but the capacitor flipping structure only requires two capacitors, in the CMOS process, the capacitor requires a large implementation area, while the capacitor flipping structure has a small implementation area. Therefore, the capacitor flipping type is more suitable for high-speed and high-precision pipeline ADC applications. The sample-and-hold circuit in this article is implemented using the capacitor flipping structure.

2. Design of Gain-Boosted Amplifier

The operational amplifier is the most important module in the entire sample-and-hold circuit. Its gain and bandwidth directly determine the accuracy and speed of the sample-and-hold circuit. However, gain and bandwidth are contradictory. High gain requires the use of multi-stage amplifiers, small bias currents, and long-channel devices; while large bandwidth requires the use of single-stage amplifiers, large bias currents, and short-channel devices. Therefore, the amplifier is a difficult point in the design of the sample-and-hold circuit.

The main operational amplifier in this paper adopts a fully differential folded cascode structure, and uses gain enhancement technology to improve the gain of the amplifier, achieving the requirements of high gain and large bandwidth [4-5]. The main operational amplifier circuit is shown in Figure 2. Since the mobility of NMOS tube is higher than that of PMOS tube, under the same transconductance, NMOS tube has a smaller area, so that the operational amplifier has a smaller input capacitance, which is beneficial to improve the feedback coefficient of the sampling and holding circuit. Therefore, this paper adopts a folded cascode structure with NMOS tube as the input pair tube. The two auxiliary operational amplifiers BN and BP are folded cascode amplifiers with NMOS and PMOS tubes as input pairs. The CMFB module in Figure 2 is the common-mode feedback circuit of the main operational amplifier. Since the output swing of the main operational amplifier is large, the switched capacitor common-mode feedback circuit shown in Figure 3 (a) is adopted. The switched capacitor common-mode feedback will not be limited by the output swing, and it only has static power consumption. For the two auxiliary operational amplifiers, since their output and input ranges are very small, the continuous time common-mode feedback circuit shown in Figure 3 (b) is adopted. This circuit has no capacitor and saves area. Figure 2(b) shows the frequency characteristic curve of the main operational amplifier when the load capacitance is 6 pF, with a gain of 133 dB, a bandwidth of about 478 MHz, and a phase margin of 59.7 degrees. The average current consumed by the entire amplifier (including the bias circuit, auxiliary operational amplifier, and common-mode feedback circuit) is 8.5 mA.

3 Design of sampling switch

The performance of the sampling switch plays a very important role in the sample-and-hold circuit. For a simple NMOS switch, its on-resistance Ron when the switch is turned on is:

It can be seen that the on-state Ron is a nonlinear resistance related to the input signal Vin, which will introduce harmonic distortion in the output signal [5]. This paper adopts the gate voltage bootstrap switch shown in Figure 4(a). The curve of the on-resistance of the switch changing with the input signal amplitude is shown in Figure 4(b). The slope of the curve is about 11 Ω/V. The on-resistance changes little with the input signal amplitude and has high linearity.

4 Simulation Results

The circuit was designed using TSMC's 0.18 μm process, with a power supply voltage of 3.3 V and a sampling clock of 40 MHz. The circuit was simulated using Spectre. A step signal of 1 V was added to the input of the sample-and-hold circuit, and the transient simulation results are shown in Figure 5. From the analysis of the figure, it can be concluded that at the end of the hold phase, the output amplitude of the sample-and-hold circuit is 1.000 08 V, with an error of 0.08 mV from the ideal voltage, and the establishment accuracy reaches 0.008%. Figure 6 shows the spectrum analysis of the signal, with a sinusoidal signal with a peak-to-peak value of 2 V and a frequency of 1.992 187 5 MHz. A 4 096-point FFT was performed on the output signal, and the results showed that its SNDR was 84.8 dB, SFDR was 92 dB, and the effective number of bits was 13.8 bits, which can meet the requirements of the 13-bit 40 MHz pipeline ADC for the front-end sample-and-hold structure. The average current consumed by the entire sample-and-hold circuit is 8.501 mA.

This paper designs a high-speed and high-precision sample-and-hold circuit, which can be used as the front-end module of a 13-bit 40 MHz pipeline ADC. The sample-and-hold circuit is a capacitor flip structure, and uses a gate voltage bootstrap switch to improve the linearity of the switch. Its operation is a gain-enhanced folded common source and common gate structure, which meets the requirements of high speed and high gain. The simulation results show that the accuracy and speed of the entire sample-and-hold circuit meet the design requirements.