NAND Flash driver design solution

NAND Flash driver design solution

Taking Samsung K9F2808UOB as an example, the interface circuit between NAND Flash and S3C2410 is designed, and the design and implementation method of NAND Flash in ARM embedded system is introduced, and verified on UBoot. The designed driver is easy to transplant and can simplify the development of embedded system.

Keywords ARM UBoot NAND Flash K9F2808UOB Driver

introduction

In the current development and design of various embedded systems, storage module design is an indispensable and important aspect. NOR and NAND are the two main non-volatile flash memory technologies on the market. NOR Flash memory has a small capacity and a slow write speed, but because of its fast random read speed, it is often used to store program codes in embedded systems. Compared with NOR, the advantage of NAND flash memory is its large capacity, but its speed is slower, because it has only 8 or 16 I/O ports, and these signals must be transmitted in turn to complete the transmission of addresses and data. NAND Flash has an extremely high cell density, can have a relatively large capacity, and is relatively cheap.

This article takes Samsung's K9F2808UOB chip as an example to introduce the design method of NAND Flash interface circuit and driver. This article introduces the basic principles of developing NAND Flash driver, aiming to simplify the embedded system development process.

1 NAND Flash Working Principle

The NAND Flash support of the S3C2410 board consists of two parts: the NAND Flash controller integrated on the S3C2410 CPU
and the NAND Flash storage chip. To access the data in the NAND Flash, you must send commands through the NAND Flash controller. Therefore, NAND Flash is equivalent to a peripheral of the S3C2410 and is not located in its memory address area.

1.1 Chip internal storage layout and storage operation characteristics

A NAND Flash is a device, and its data storage is hierarchical: 1 device = 4 096 blocks; 1 block = 32 pages; 1 page = 528 bytes = data block size (512 bytes) + OOB block size (16 bytes). In each page, the last 16 bytes (also known as OOB, Out?of?Band) are used to set the status after the NAND Flash command is executed, and the remaining 512 bytes are divided into the first half and the second half. The first half, the second half, and the OOB can be located respectively through the NAND Flash command 00h/01h/50h, and the pointer built into the NAND Flash points to their respective first addresses.

The characteristics of storage operation are as follows: The minimum unit of erase operation is block; each bit of NAND Flash chip can only change from 1 to 0, but not from 0 to 1, so the corresponding block must be erased before writing to it (erasing means changing all bits of the corresponding block to 1); the 6th byte (ie 517 bytes) of the OOB part marks whether it is a bad block. If the value is FF, it is not a bad block, otherwise it is a bad block. In addition to the 6th byte of OOB, usually at least the first 3 bytes of OOB are used to store the NAND Flash hardware ECC code.

1.2 NAND Flash Interface Circuit

First, the hardware design of the development board is introduced. Figure 1 shows the NAND Flash interface circuit. When switches 1 and 2 are connected, R/B indicates ready/busy. When switches 2 and 3 are connected, nWAIT can be used to add additional waiting cycles for read/write access. The NAND Flash controller has been integrated in the S3C2410 processor. Figure 2 shows how the microcontroller connects to the NAND Flash.

Figure 1 NAND Flash interface circuit

1.3 Controller Working Principle

The NAND Flash controller maps its own special function registers in its dedicated register area (SFR) address space, which is to write the built-in commands of the NAND Flash chip into its special function registers to realize the reading, verification and programming control of the NAND Flash chip. The special function registers are: NFCONF, NFCMD, NFADDR, NFDATA, NFSTAT, NFECC.

Figure 2 NAND Flash and S3C2410 connection circuit

2 Flash programming program principle and structure

Basic principle: Write the data in a storage area in SDRAM to the NAND Flash storage space. The burning program is completed in three layers vertically. The first layer: the main burning function, writes the data in a storage area in SDRAM to the NAND Flash storage space. The second layer: This layer provides page read, write and block erase functions for NAND Flash operations. The third layer: provides the core functions for the second layer to operate the special function registers in the specific NAND Flash controller. This layer is also the function that actually transfers data between SDRAM and NAND Flash. The second layer is the key to the design of the driver. The following is a detailed introduction to the read, write (also known as programming) and erase function coding of this layer.

2.1  NAND Flash Read

Function: The data read operation is in pages. When reading data, first write the read data command 00H, then enter the address of the page to be read, then read the data from the data register, and finally perform ECC check.

Parameter description: block, block number; page, page number; buffer, points to the starting position to be read into the memory; return value 1: read successful, return value 0: read failed.

static int NF_ReadPage(unsigned int block, unsigned int page, unsigned char *buffer){
NF_RSTECC(); /* Initialize ECC */
NF_nFCE_L(); /* Chip select NAND Flash chip*/
NF_CMD(0x00); /* Read from area A*//* A0~A7(column address) */
NF_ADDR(0); /* A9A16(page address) */
NF_ADDR(blockPage&0xff); /* A17A24,(page address) */
NF_ADDR((blockPage>>8)&0xff);/* A25, (page address) */
NF_ADDR((blockPage>>16)&0xff);/* Wait for NAND Flash to be in re-prepare state*/
ReadPage();/* Read the whole page, 512 bytes*/
ReadECC();/* Read ECC code*/
ReadOOB();/* Read the OOB block of this page*//* Uncheck NAND Flash*/
NF_nFCE_H();/* Check ECC code and return*/
Return (checkEcc())}

2.2  NAND Flash Program

Function: Program the page, used for write operation.

Command code: First write 00h (A zone)/01h (B zone)/05h (C zone), indicating which zone to write to; then write 80h to start programming mode (write mode), then write address and data; finally write 10h to end programming. Figure 3 is the program flow chart.

Figure 3 Program writing process

Parameter description: block, block number; page, page number; buffer, points to the starting position of the data to be written to the NAND Flash in the memory; return value 0, write error, return value 1, write success.

static int NF_WritePage(unsigned int block, unsigned int page, unsigned char *buffer){
NF_RSTECC(); /* Initialize ECC */
NF_nFCE_L(); /* Chip select NAND Flash chip*/
NF_CMD(0x0); /* Start writing from area A*/
NF_CMD(0x80); /* Write the first command*//* A0~A7(column address) */
NF_ADDR(0);/* A9A16(page address) */
NF_ADDR(blockPage&0xff);/* A17A24(page address) */
NF_ADDR((blockPage>>8)&0xff); /* A25(page address) */
NF_ADDR((blockPage>>16)&0xff);/* Write page 512B to NAND Flash chip*/
WRDATA(); /*OOB has 16 bytes in total. What to store in each byte is defined by the programmer. ECC check code is stored in Byte0 and Byte2, and bad block flag is stored in Byte6*/
WRDATA(); /* Write the OOB data block of this page*/
CMD(0x10); /* End write command*/
WAITRB();/* Wait for NAND Flash to be in ready state*//* Send read status command to NAND Flash */
CMD(0x70);
if (RDDATA()&0x1) { /* If there is an error in writing, mark it as a bad block and cancel NAND Flash selection*/
MarkBadBlock(block);
return 0;
} else { /* Exit normally and cancel NAND Flash selection*/
return 1;}

2.3  NAND Flash Erase

Function: Block erase command.

Command code: First write 60h to enter the erase mode, then enter the block address, and then write D0h to indicate the end of the erase.

Parameter description: block, block number; return value 0, erasure error (if it is a bad block, it will return 0 directly; if an error occurs during erasure, it will be marked as a bad block and then return 0); return value 1, successful erasure.

static int NF_EraseBlock(unsigned int block){/* If the block is a bad block, return*/
if(NF_IsBadBlock(block)) return 0;
NF_nFCE_L(); /* Chip select NAND Flash chip*/
NF_CMD(0x60); /* Set erase mode*//* A9A16(Page Address) , is based on block erase*/
NF_ADDR(blockPage&0xff);
NF_ADDR((blockPage>>8)&0xff); /* A25(Page Address) */
NF_ADDR((blockPage>>16)&0xff); NF_CMD(0xd0); WAITRB();CMD(0x70); if(RDDATA()&0x1){/* If there is an error, mark it as a bad block and cancel the Flash selection*/ MarkBadBlock(block); return 0; } else { /* Exit, uncheck Flash*/ return 1;}

3 ECC Check Principle and Implementation

Since the NAND Flash process cannot guarantee that the NAND Memory Array maintains reliable performance during its life cycle, bad blocks will be generated during the production and use of NAND. In order to detect the reliability of data, a certain bad block management strategy is generally adopted in the system using NAND Flash, and the premise of managing bad blocks is to be able to detect bad blocks relatively reliably. If there are no problems with the operation timing and circuit stability, when NAND Flash fails, it will generally not cause the entire block or page to be unable to read or all errors, but only one or several bits in the entire page (for example, 512 bytes) will be wrong. Commonly used data checks include parity check and CRC check, and in NAND Flash processing, a special check is generally used - ECC. ECC can correct single-bit errors and detect double-bit errors, and the calculation speed is very fast, but it cannot correct errors of more than 1 bit, and it is not guaranteed to detect errors of more than 2 bits. ECC generally generates 3 bytes of ECC check data for every 256 bytes of original data. These 3 bytes, a total of 24 bits, are divided into two parts: 6 bits of column check and 16 bits of row check, and the redundant 2 bits are set to 1, as listed in Table 1.

Table 1 Calibration data composition

First, we will introduce the ECC column checksum. The ECC column checksum generation rule is shown in Figure 4. "^" represents the "bitwise XOR" operation. Due to space constraints, the row checksum is not introduced. Interested readers can refer to the chip datasheet, which can be downloaded for free on the Samsung website.

Figure 4 Column validation and generation rules

The mathematical expression is:

When writing data to a NAND Flash page, an ECC checksum is generated for every 256 bytes, called the original ECC checksum, and saved in the OOB data area of ​​the page. When reading data from NAND Flash, an ECC checksum is generated for every 256 bytes, called the new ECC checksum. When checking, it is not difficult to infer based on the above ECC generation principle: the original ECC checksum read from the OOB area is XORed with the new ECC checksum bit by bit. If the result is 0, it means there is no error (or an error that cannot be detected by ECC); if 11 bits in the 3-byte XOR result are 1, it means there is a bit error and it can be corrected; if only 1 bit in the 3-byte XOR result is 1, it means an error in the OOB area; other cases indicate an error that cannot be corrected.

4 Functional verification under UBOOT

The main way to implement UBOOT's support for NAND Flash is to implement NAND Flash operations under the command line. The commands implemented for NAND Flash are: nand info, nand device, nand read, nand write, nand erase, nand bad. The main data structures used are: struct nand_flash_dev and struct nand_chip. The former includes information such as the main chip model, storage capacity, device ID, I/O bus width, etc., and the latter is the information used for specific operations on NAND Flash. Since the method of porting the driver to UBoot is not the focus of this article, it will not be introduced in detail.

Verification method: Download data to SDRAM via TFTP, and use the nand read, nand write, and nand erase commands to read, program, and erase the NAND Flash. The test results are listed in Table 2. Compared with the data in the datasheet, it can be concluded that the driver runs well in the system.

Table 2 Test results

Conclusion

Nowadays, embedded systems are increasingly widely used, and storage devices are an indispensable part of embedded systems. NAND Flash has obvious advantages over other storage devices when the capacity does not exceed 4 GB. The driver designed in this paper is not based on any operating system and can be easily ported to multiple operating systems and Boot Loaders, which has certain practical significance for simplifying the development of embedded systems.