A Design Scheme for Taxi Fare Meter

introduction

EDA enables users to design and analyze circuits without the need for actual chips, circuit boards, and instruments. It uses in-system programming technology to logically reconstruct and upgrade the system on site, thus realizing the softwareization of hardware design.

EDA technology uses programmable logic devices FPGA and CPLD and their development systems as hardware platforms, and EDA development software such as Max+PlusⅡ as development tools to design digital systems based on a hierarchical design method of logical function modules. Max+PlusⅡ design can use multiple input methods such as schematics and hardware description languages ​​(VHDL), and supports any mixed design of these files. Different input methods can be used for design at different levels. Since VHDL is good at describing the logical functions of modules, VHDL is often used to describe the bottom-level module design, while schematics are good at describing the connection relationship between modules, so schematic input methods are often used in top-level design.

Taxi meters generally adopt a design method based on a single-chip microcomputer, which is not flexible and convenient enough. To this end, this paper introduces a method of designing a taxi meter using a hierarchical design method using EDA technology. That is, VHDL is used to write each functional module to achieve low-level design; the relationship between each module is described by schematic input to achieve top-level design. FPGA programmable logic devices are used as system control units, and there is no need to add peripheral circuits. To update functions, only the software needs to be modified. Experiments show that this design method is simple and fast, and the performance of the designed system is reliable. The digital electronic system designed using this method has strong flexibility.

1 Taxi meter function

Functional requirements of taxi meters:

(1) Taxi drivers are charged based on mileage, with a starting fee of RMB 7.0;

(2) After driving 3 km, the charge will be 2 yuan/km. No charge will be made when the vehicle is parked.

(3) It can preset the starting fee and the charge per kilometer, and can simulate the car's starting, stopping, speed and other states.

According to the characteristics of VHDL, designers no longer need to consider selecting standard chips with fixed functions, but instead establish a taxi meter system module based on the realization of system functions and performance, as shown in Figure 1.

2 Design and Implementation of Taxi Meter

The system is designed in two levels: bottom level and top level. The bottom level design uses VHDL to write each functional module, and the top level design uses schematic diagrams to describe the connections between modules.

2.1 Design of underlying files

The bottom-level modules include: taxi speed control module; meter mileage counting module; meter billing counting module.

Take the taxi speed control module as an example.

The taxi speed control module is used to control the speed of the taxi. In Figure 1, when the start/stop switch and the reset signal RESET are both "1", the car starts to enter the mileage counting and meter working state. By changing the input value of the "speed selection" terminal, the speed of the car can be controlled. Use CLK6 as the clock input of the speed control module, CLOCK6 as the output, and A and B as the speed selection variables. When the values ​​are from "00" → "01" → "10" → "11", the speed becomes faster and faster. The VHDL program code is as follows:

After the above program code is compiled, the corresponding module symbol is generated, as shown in Figure 2, for calling during the top-level design.

The waveform of the program after timing simulation is shown in Figure 3.

2.2 Top-level schematic design

The top-level design adopts the schematic input method. The top-level file design is realized by calling the generated module symbols and connecting them appropriately. The top-level design circuit of the taxi meter is shown in Figure 4.

In Figure 4, ko1 and ko2 are vehicle speed control switches; clk is a clock signal; reset is a reset signal; up_down is a start/stop control signal; count is a signal for preset charges per kilometer; load is a preset enable signal; dd is a preset starting fee signal; out5 and out4 are integer digits for recording mileage; out6 is decimal digits for recording mileage; outl and out2 are integer digits for recording fees; and out3 is a decimal digit for recording fees.

2.3 Top-level file simulation and download

After the top-level schematic is compiled, the top-level file is generated. After the top-level file is simulated and the result is correct, it is downloaded using Altera's FPGA chip EPF10K3LC84-3 and its SE-5M development system. The download result shows that the designed taxi meter fully meets the design requirements.

3 Conclusion

Since the internal circuit of the new device is constructed by program and the logical relationship of the hardware is described by language, the logical relationship of the hardware can be modified by simply modifying the statement. It can be seen that this design method can greatly improve work efficiency, make the design more flexible and fast, reduce the number of devices, avoid complex wiring, reduce the size of the system, reduce consumption, and improve the reliability, inheritance and transplantability of the system.