How to realize 3D integrated circuits

Early IEEE Fellows Saraswat, Rief, and Meindl predicted that "chip interconnection may slow down or even stop the historical development of the semiconductor industry..." and first proposed that 3D integration technology of circuits should be explored.

In September 2007, the Semiconductor Industry Association (SIA) announced that "the ability to reduce transistor size will be limited by physical limitations within the next 10-15 years or so", so the need for 3D integration became more obvious. Completely new device structures, such as carbon nanotubes, spintronics, or molecular switches, will not be ready for another 10-15 years. 5 New assembly methods, such as 3D integration technology, have been proposed again.

The memory speed lag is another driver of 3D integration. It is well known that memory access speeds are slow relative to processor speeds, causing the processor to be stalled while waiting for data from the memory. This problem is exacerbated in multi-core processors, which may require the memory to be directly bonded to the processor.

3D IC Integration Technology to the Rescue

In February 2005, when ICs Going Vertical was published, few readers were aware of the technological advances taking place in 3D IC integration, which they viewed as just lamination and wire bonding, a back-end packaging technology.

Today, 3D integration is defined as a system-level integration structure in which multiple layers of planar devices are stacked and connected in the Z direction via through-silicon vias (TSVs) (Figure 1).

Many processes have been developed to manufacture such laminated structures, and the following are the key technologies:

■ TSV fabrication: Z-axis interconnects are connections that penetrate the substrate (silicon or other semiconductor materials) and are electrically isolated from each other. The size of the TSV depends on the data acquisition bandwidth required on a single layer;

■ Layer thinning technology: Initial applications need to be thinned to about 75~50μm, and in the future it needs to be thinned to about 25~1μm;

■ Alignment and bonding technology: either between chip and wafer (D2W) or between wafer and wafer (W2W).

3D IC integration can eliminate a large portion of the packaging and interconnection processes by inserting TSVs, thinning, and bonding. However, it is not yet completely clear where these need to be integrated in the overall manufacturing process. It seems that for TSV processes, they can be obtained through IDMs or wafer fabs during IC manufacturing and thinning, while bonding can be achieved by IDMs or by external semiconductor assembly and test providers (OSATS) in packaging operations, but this is likely to change as the technology matures.

What is likely to happen in the future is that 3D IC integration technology will begin when the development paths between IC manufacturing and packaging overlap.

3D process selection

TSVs can be made during the IC manufacturing process (via first) or after IC manufacturing is completed (via last). In the former case, front-end interconnect (FEOL) type TSVs are made before the IC wiring process begins, while back-end interconnect (BEOL) type TSVs are implemented in the IC manufacturing plant during the metal wiring process.

FEOL-type vias are fabricated on blank silicon wafers before all CMOS processes begin (Figure 2). The conductive material used must be able to withstand the thermal shock of subsequent processes (usually above 1000°C), so only polysilicon can be used. TSVs made during the BEOL process can use metal tungsten or copper, and in general, the manufacturing process is early in the entire integrated circuit process to ensure that TSVs do not occupy valuable interconnect wiring resources. In both FEOL and BEOL cases, TSVs must be designed into the IC wiring.

TSVs can also be made after the CMOS device is fabricated. It can be done before the bonding process, or after the bonding process. Since the CMOS device is already fabricated, the wafer does not need to be subjected to high temperature processing when the vias are formed, so copper conductive materials can be used. Obviously, the blank area for making these vias needs to be considered when designing the chip.

If the choice is available, making TSVs in the foundry is a relatively simple option, whether it is a FEOL or BEOL solution. The BEOL interconnect layer is a complex mixture of different dielectric and metal layers. Etching through these layers is difficult and product-specific. Making TSVs by etching through the BEOL layers after full IC manufacturing will block the wiring channels, increase wiring complexity and increase chip size, and may require an additional wiring layer. Now that foundries such as TSMC (Taipei, Taiwan) and Chartered (Singapore) have announced their intention to mass-produce TSV manufacturing, making the vias in the IC manufacturing process will become a more viable option.