The Construction of Wireless Data Transmission Network for Shortwave Radio

Radio shortwave refers to electromagnetic waves with a wavelength of 10 to 100 m and a frequency of 3 to 30 MHz. Using shortwave channels for data communication has the advantages of long transmission distance, less terrain restrictions, and less prone to human damage, and has broad application prospects. Based on the analysis of the characteristics of shortwave channels, this paper improves the shortwave radio station, the main tool for shortwave communication, and proposes a scheme for building a point-to-multipoint star topology wireless network for long-distance data transmission. Based on this scheme, the system software and hardware based on DSP chips are designed. Through experimental testing, the system realizes the networking function.

1 Networking Solution

When designing a networking solution, it is necessary to improve the shortwave radio . In order not to affect the original internal hardware structure and function of the radio, this paper designs the hardware that interfaces with the audio input and output ports of the shortwave radio. The digital signal is first modulated by audio at the transmitting end, and then the radio performs secondary modulation to the shortwave frequency band for transmission. At the receiving end, the digital signal is obtained through shortwave demodulation and audio demodulation. This improved method is suitable for most radio stations with voice communication functions, is easy to transplant, and has good economy and versatility.

Time Division Multiple Access (TDMA) is used, and only one user sends a signal at a time to obtain better signal-to-noise ratio performance. The multipath delay generated in shortwave communication generally limits the code rate to below 200 b/s. This scheme sets the code rate to 100 b/s.

The multi-level frequency keying (MFSK) audio modulation method is selected. This method is suitable for data transmission on channels lacking phase stability and fading channels, and fully utilizes the transmission bandwidth to improve the transmission rate. At the receiving end, the MFSK signal is demodulated using the non-coherent demodulation and square rate detection method [1]. This method does not require the estimation of the carrier phase, which greatly reduces the complexity of the system.

The transmitter inserts a time domain bit synchronization pilot before sending the MFSK signal to help the receiver obtain the bit synchronization information of the sampling decision. This scheme uses the characteristic that the autocorrelation function of the m-sequence is similar to the impulse function, and uses the m-sequence audio modulation signal with the same period as the code element as the bit synchronization pilot. When the receiver performs pilot detection, it first sequentially shifts the sampled signal, and then correlates it with the local sequence. Within a code element period, it finds the maximum correlation result and the corresponding time, and considers this time as the end of the code element, and thus obtains the bit synchronization information.

2 System Hardware Design

2.1 Overall structure of system hardware

The system hardware is based on DSP chip, mainly performs digital processing on the signal, combines fixed hardware structure with flexible software algorithm, and can improve the scheme and upgrade the system by modifying the software, which is flexible, simple, convenient and easy. The system uses the DSP chip TMS320VC5402 (referred to as C5402) produced by TI, which is a low-power, cost-effective 16 b word length fixed-point DSP chip with a computing rate of up to 100MI/s. It has highly flexible operability and high-speed processing capability, and has been widely used in real-time embedded voice communication and other aspects.

The hardware structure of the system is shown in Figure 1. It mainly includes four modules: DSP module, power module, analog interface module, asynchronous serial interface and EPROM module. The DSP module is used to complete the digital signal processing algorithm; the power module uses the 12 V DC voltage provided by the radio, and after two-stage power conversion, it generates stable 3.3 V and 1.8 V voltage outputs, which are provided to C5402 as I/O power and core power respectively. At the same time, the 5 V DC voltage also powers other chips on the circuit board; the analog interface module is connected to the radio audio port to sample the audio output signal and generate the audio analog input signal, and control the radio audio input and output conversion keying signal PTT; the asynchronous serial interface and EPROM module completes the communication with the information entry device, as well as saves the program code and loads it automatically when reset.

2.2 Analog interface module design

The system hardware uses a 10 b parallel A/D converter TLV1571, which has a sampling rate of up to 1.25 MS/s, extremely low power consumption, and has two software-configurable control registers. All sampling, conversion, and data output are controlled by a trigger signal, and the interface and control are simple. It uses a dual-channel 8 b parallel D/A converter TLC7528, which is designed to have a separate on-chip data latch, with a setup time of 100 ns when VDD = 5 V, a transmission delay of 80 ns, and can work in bit voltage mode. Data latching and digital-to-analog conversion are also fully controlled by trigger signals. Their connection with C5402 is shown in Figure 2.

This module maps TLV1571 and TLC7528 to 0x0002 and 0x0001 of I/O space respectively through address decoding, ensuring that only one chip is in the strobe state when C5402 accesses the data bus. At the beginning of the program, the working mode of TLV1571 should be initialized. By writing control words 0x00C0 and 0x0100, it is configured to use the internal clock, software start sampling, and binary output mode [2]. C5402 sets the serial port pin FSX0 as a general output pin to control the read signal of TLV1571. In each timer interrupt, a corresponding trigger signal is generated to start D/A and A/D conversion. By changing the frequency of the timer interrupt, the sampling rate and D/A conversion frequency can be flexibly changed.

2.3 Asynchronous serial interface and EPROM module design

The connection between the asynchronous serial interface and the EPROM module and C5402 is shown in Figure 3.

This scheme uses two pins of the buffered serial port McBSP0 of C5402: BDR0 and BDX0 as general input and output pins to simulate asynchronous serial port, and uses MAX232 chip to convert the TTL level output by C5402 into a level that conforms to the RC232 standard, so that it can communicate with devices that comply with this standard. The EPROM chip uses AT29C512, which has a storage capacity of 64 k×8 b, and is used to store program code and complete boot loading.

3 System Software Design

3.1 Overall flow of system software

At the beginning of the program, it is necessary to initialize and set some initial values ​​and hardware status, and then enter the process of data transmission and reception. The receiving center first sends a "query" signal to start a data reception and provide a timing benchmark for the entire communication network. After the user detects the "query" signal, if there is data to be sent, the data is sent within its own time period. The receiving center continuously sends "query" signals at certain time intervals, thereby realizing two-way data transmission. The software process is shown in Figures 4 and 5 respectively.

3.2 Signal detection algorithm flow

Assuming the sampling rate is f samples/s and the symbol rate is Rb/s, the number of points obtained by sampling each symbol is: N = f/R. A sliding window with a length of N is set in the DSP's RAM to store the sampling results. After each sampling, the oldest sample in the sliding window is overwritten with a new sample to update the data. The N-point local pilot sequence obtained by digitizing the pilot signal and the N×M local MFSK sequence obtained by digitizing the MFSK signal are pre-stored in the RAM, and an N-point buffer is opened to store the relevant results when doing pilot detection. The flow of the signal detection algorithm is shown in Figure 6.

4 Experimental test results

Based on the networking plan and the designed software and hardware, the author used a border and coastal defense shortwave radio produced by a PLA factory to build a star network with 3 users and 1 receiving center, and tested the networking plan on this network.

The experiment sets the baud rate to 100 Baud, uses 4FSK signal modulation, and the bit rate reaches 200 b/s; the length of the m sequence is selected to be 15, and a 20-cycle bit synchronization pilot is inserted before each data signal. In order to prevent missed detection and false alarm of the synchronization pilot at the receiving end, the method of non-coherent demodulation of the received signal is adopted after continuously detecting 8 cycles of the pilot signal, and judging whether the data signal has started according to the value of the square sum result output by the square rate detector. According to the length of the user data, each user is allocated a timing time of 1 s to realize multi-user networking.

The test results show that the shortwave radio wireless data transmission network can accurately send and receive information and realize the networking function.

5 Conclusion

Using shortwave radio to build a wireless data transmission network is a task with practical significance. Starting from the characteristics of shortwave channels and shortwave radios, this paper proposes a networking solution using time division multiple access (TDMA), time division duplex (TDD), and multi-level frequency keying (MFSK), and designs the system software and hardware based on DSP chips according to this solution. Experiments have proved that the system has completed the networking function. This solution has been applied in the early warning information network established by a certain unit of the People's Liberation Army.