Digital recording system based on K9F6408U0A and SPDS202A

K9F6408U0A is a 64Mbit NAND flash memory produced by Samsung. It has the advantages of low operating voltage, fast erase speed and small size. SPDS202A is a voice chip produced by Taiwan Lingyang Company. This paper introduces a digital recording system with SPDS202A as the core , and also introduces the specific method of realizing the copy function between two K9F6408U0A chips. Finally, the relevant hardware interface and software program are given.

1 K9F6408U0A Performance Overview

The biggest advantage of K9F6408U0A is that its commands, data and addresses can communicate with the main controller through 8 I/O lines. This greatly simplifies the wiring of the system and enhances the stability of the system. In addition to the 8 I/O lines, K9F6408U0A also includes the following control lines, which can easily realize the control of K9F6408U0A by the system main controller. They are:

CLE: Command latch enable terminal, high level is valid. At the rising edge of the WE signal, the command signal can be locked into the command register through the I/O port.

ALE: Address latch enable terminal, high level is valid. At the rising edge of the WE signal, the address signal can be latched into the address register through the I/O port.

CE: Chip select line, low level is valid. During page programming or block erase operation or when the device is busy, CE high level will be ignored.

WE: Write enable port, commands, addresses and data are locked on the rising edge of the WE signal.

RE: Read enable port. The falling edge of this port sends data to the I/O port line and increases the internal column address register by 1.

WP: Write protection port, low level is effective. When it is low, programming and erasing operations are prohibited.

R/B: Operation status indication signal. When it is low, it indicates that programming, erasing or reading operation is in progress, and it becomes high after the operation is completed.

2 SPDS202A Introduction

SPDS202A is a voice chip with a high cost performance ratio produced by Taiwan SUNPLUS Company. It can be easily interfaced with the host. The host can control the recording and playback functions of the voice chip by sending command codes. It has the following features:

●It is a single-chip audio/speech coding/* chip, using SACM-S480 or SACM-S3200 compression and decompression algorithms. It has an 8kHz sampling rate and its data low bit rate is 4.8kbps or 32kbps;

●With digital volume control function;

●It has FLASH management function and can automatically manage FLASH data internally. Its standard FLASH interface can connect up to 4 FLASH chips, totaling 64Mbit.

●Using the UART interface, it can be easily connected to a PC and other RS232 devices, and data can be easily uploaded or downloaded;

●Built-in phase-locked loop circuit;

●Embedded high-quality 10-bit 8kHz ADC and DAC;

●Low power consumption, using 2.8V ~ 3.6V operating voltage.

Because SPDS202A has the above characteristics, only a few peripheral circuits need to be added to form a large-capacity voice recording and playback system.

3 Composition of digital recording system

The structure diagram of the digital recording system with SPDS202A as the core and Winbond's W78E58 as the main controller is shown in Figure 1. W78E58 is compatible with MCS-51 series microcontrollers. Its built-in 32kflash EEPROM can be used as program memory, and the built-in 256-byte SRAM is very suitable for the magnetic programming operation of K9F6408U0A.

Figure 2 shows the hardware interface circuit of W78E58 and SPDS202A. In the figure, TADCE is the chip select signal line, which can latch the command/data on its rising edge. TADSEL1 and TADSEL0 are command select signal lines, and their functions are listed in Table 1.

Table 1 Functions of command selection signal lines

TADD7~TADD0 are 8-bit data lines. When it is working, the SPDS202A of the main controller sends three bytes of data, of which the first byte is always 0FFh, the second byte is the low byte of the command code, and the third byte is the high byte of the command code; then the main controller receives two bytes of data returned from SPDS202A. The communication program between the two is as follows (written in C51):

Void Mcu_202_Comm(void) /*MUC and SPDS202A communication program*/

{via=0xFF; /*The first byte is 0FFh*/

SendOneData() ; /*Call the subroutine to send one byte of data*/

Via=CMDL; /*The second byte sends the command code low byte*/

SendOneData() ;

Via_CMDH; /*The third byte sends the high byte of the command code*/

SendOneData() ;

ECHOL=ReadOneData(); /*Read return data*/

ECHOH=ReadOneData();

}

The following is an example of how the system works.

Void Record(void)

{CMDL=0x00; /*Send recording command code*/

CMDH=0x10;

Mcu_202_Comm() ;

If(Err=1) /*If an error occurs, return*/

{Err=0;

return;

}

}

It can be seen that the system implements its functions by sending a series of control command codes to SPDS202A by the main controller.