Application of MAX121 chip in high-speed serial interface circuit

1 Performance and features of MAX121 chip

 The MAX121 chip is a 14-bit analog-to-digital conversion integrated circuit (ADC) with a serial interface. It contains a bottom-overflow, bottom-noise, and buried Zener voltage reference power supply with a track/hold circuit. It has fast conversion speed, low power consumption, sampling rate up to 308 ks/s, full-scale input voltage range of ±5V, and power consumption of 210 mW. Interfacing directly with the serial interfaces of most popular digital signal processors, this input can accept signal levels in TTL or CMOS with clock frequencies of 0.1-5.5MHz. 

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 The functional block diagram of the MAX121 chip is shown in Figure 1. It has 16-pin and 20-pin modes, 16-pin is available in DIP and SO packages, and 20-pin is available in SSOP package. The characteristics are as follows: 

    14-bit resolution; 2.9 μS conversion time/308 ks / s throughput; 400 ns sampling time; Noise floor and low distortion: 78Db SINAD  -85Db THD; ±5V bipolar input range, withstands ±15V transients voltage; 210 mW power consumption; continuous conversion mode available; 30 ppm/C, -5V internal reference source; interfaces with DSP processors; 16-pin DIP and SO packages, 20-pin SSOP packages.

 Limit parameters: V _DD to DGND 0.3-+6V; V _SS to DGND +0.3--7V; AIN to AGND ±15V; AGND to DGND ±0.3V digital input to DGND (CS, CONVST, MODE, CLKIN, INVCLK, INVFRM); -0.3(V _dd +0.3V); Digital output to DGND (SFRM, FSTRT, SCLK, SDATA) +0.3(V _dd +0.3V); Continuous power consumption (TA ₌ +70 ℃)

 Strength exceeding the above limit parameters may cause permanent damage to the device. These are extreme parameters only and do not imply that the device will operate effectively under extreme parameter conditions or under any other operating conditions beyond those specified in the technical specifications. Extended operation time under extreme parameter conditions will affect the reliability of the device.

2 working circuit

 MAX121 uses successive comparison technology and track/hold (T/H) circuits to convert analog signals into 14-bit serial data output codes. Its control logic interfaces easily to most microprocessors and digital signal processors (DSPs), requiring only a few passive components in most applications. The T/H circuit does not require external capacitors.

2.1 Analog input tracking and holding

 Based on equivalent input circuit analysis, the sampling structure of the analog comparator of ADC is given. An internal buffer charges the holding capacitor to reduce the acquisition time required during conversion. The analog input presents a 6k input resistor and a 10pF capacitor in parallel with it.

 Between conversions, the buffer input is connected to the AIN terminal through the input resistor. When conversion begins, the buffer is disconnected from the AIN terminal and the input signal is sampled. At the end of the conversion, the buffer input is connected back to AIN and the capacitor is kept tracking the input voltage. Whenever a conversion is not in progress, the T/H is in tracking mode. After the conversion begins, the holdover mode startup time is approximately 10 ns (window delay). The typical time to change in latency from one conversion to the next is 30 ps (window jitter).

2.2 Circuit clock frequency

 MAX121 requires a clock compatible with TTL and CMOS levels when working, and the clock frequency ranges from 0.1-5.5 MHz. To meet the 400 ns acquisition time requirement for 2 clock cycles, the maximum clock frequency is limited to 5MHz. Due to the limitation of the internal T/H voltage drop rate, the clock frequency in all modes should not be lower than 0.1MHz.

2.3 Output data format

 The conversion result is output as a 16-bit serial data stream, the first 14 bits are data bits (MSB first), and the last 2 bits are zero. The output data is in two's complement form. On the rising edge of CLKIN, data is output synchronously on the SDATA terminal.

 The output data can be framed using FSTRT or SFRM output. FSTRT (normally low) goes high 1 clock cycle below MSB. The SDATA terminal outputs the MSB on the falling edge of FSTRT.

 When the SFRM output (usually high when INVFRM=V _dd ) becomes low, the MSB appears on the SDATA terminal. SFRM becomes high level after 16 clock cycles. The polarity of the SFRM can be reversed by connecting the input to digital ground. A minimum of 18 clock cycles per conversion is required to obtain valid SFRM output.

 If there are several devices sharing the serial bus, you can refer to the data access and data retention timing in Figure 2. 

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3 TMS320 high-speed serial interface

3.1 Initialization after power-on

 If the following conditions are met, the first conversion of MAX121 after power-on will be valid. Provides 16 clock pulses to put the T/H into tracking mode, plus a minimum time of 400 ns for data acquisition in tracking mode. Make sure the reference source has stabilized. The settling time for each 1 μF reference bypass capacitor is 0.5 ms (11ms for a 22 μF capacitor ).

3.2 Serial clock maximum rate

 When interfacing with a digital signal processor, the maximum serial clock rate of the MAX121 depends on the minimum setup time required by the processor's serial data input and the maximum delay time of the ADC's clock and data. The MAX121 has two methods of reading data into the processor. CLKIN is the input clock of MAX121, and SCLK is the serial clock that shifts data into the processor, supporting asynchronous data transmission. t _SU is the minimum data establishment time required by the processor's serial data input; t _CD is the maximum delay time from CL KIN to SCLK of MAX121; t _SC is the maximum delay time from SCLK to SDATA of MAX121. The MAX121's SCLK output drives the processor's serial interface, which removes tCD from the above agenda _and allows the use of faster clock frequencies. In this case, the maximum serial clock speed is calculated by:

 f _CLKIN =1/2(t _SU +t _SC )

3.3 High-speed data serial interface

 The flexibility of MAX121 allows it to be connected with various serial interfaces of Texas Instruments TMS320. The high-speed interface allows the MAX121/TM320 system to obtain the maximum data throughput rate when the MAX121 works at its fastest clock. Figure 3 shows the wiring required to complete this interface. Figure 4 is the timing diagram of the interface. 

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 The CLKIN of MAX121 is driven by an external clock oscillator. The XF0 I/O port of TMS320 drives the MAX121 input low to start a conversion. The CLKR (receive clock) terminal of the TMS320 is configured as an input and driven by the SCLK output of the MAX121. The data at the SDATA output of the MAX 121 changes state on the rising edge of the clock, and on the falling edge of the clock, the data is latched into the DR input of the TMS320. This provides 1/2 clock cycle to meet the data setup and hold times required at the TMS320DR input. The maximum skew between the MAX121SCLK and SDATA is 65ns at +25, so 1/2 clock cycle is sufficient to meet the required setup and hold times.

 The FSTRT output of the MAX121 drives the FSR input of the TMS320 to frame the data. A falling edge on the FSTRT output indicates that the MSB is ready to be latched. On the next falling clock edge, the MSB is latched in TMS320. Using this interface, TMS320 can receive 16-bit words (RLEN=01 in the TMS320 serial port overall control register), so the 14-bit data is clocked into the DSP synchronously, followed by two trailing 0s.

4 Conclusion

 In recent years, with the increasing number of portable and handheld electronic products, the application of MAXIM series products has become more and more extensive. Here is a detailed introduction to the application of MAX121 chip in digital signal processing high-speed serial interface circuits. At the same time, the MAX121 integrated circuit is also widely used in fields such as language recognition and synthesis, DSP servo synthesis, and spectrum analysis. 

References

1 Zheng Yuqiang, Xu Ziwen MAXIM Integrated Circuit User Manual. Beijing: People's Posts and Telecommunications Press, 1988, 1

2 Signal Processing Society of China Electronics Association (Translated). Digital Signal Processing Program Library. Beijing: Tsinghua University Press, 1988
3 Wang Jianxin. TMS320 Digital Signal Processor and Application. Nanjing: Nanjing University of Science and Technology Press, 1994, 10

Source: modern electronic technology