Four Basic Principles of Analog BIST

introduction

The working principle of digital BIST is to use a LFSR (linear feedback shift register) to generate a pseudo-random bit pattern, and then apply this bit pattern to the circuit under test through a trigger that is temporarily configured as a serial shift register. Digital BIST also uses the same trigger to capture the response, compress the shifted result into a digital mark, and then compare it bit by bit with a correct mark.

1 Definition of “Simulation”

"Analog" circuits mean different things to different people. A PLL or SERDES (serializer/deserializer) can be considered digital, analog, or mixed-signal. BIST testing of these units can be purely digital, since these functions have only digital inputs and outputs. For example, some ICs will use an on-chip frequency counter.

To measure the output frequency of a PLL, it uses a known number of cycles of a reference frequency to count the number of cycles of oscillation. If any bit in the count is different from the expected value, the test fails. Many methods used to test the performance of IC SERDES transceivers use looped back pseudo-random data, such as detecting a bit error, which is considered a failure. However, when testing analog circuits such as ADCs or DACs, it is obviously required that the BIST circuit can generate or capture analog signals, that is, signals where the instantaneous voltage is always related. Traditional analog circuits (such as filters and linear regulators) have analog inputs and outputs, but many have digitally controlled signals or clocks. The purest analog circuits (such as RF circuits) may not have digital signals at all.

When testing, analog circuits must have at least one signal with a non-deterministic transient voltage. Testing includes checking whether the signal is between two voltages, a digital value, or a time threshold; checking whether the signal statistics are within the limits; or checking whether an arithmetic operation value of the relevant signal is between the limits. For all circuits with any analog signal, the analog test principle should be used.

The response of a purely digital circuit is deterministic, so an acceptable output signal only needs to be sampled once. However, if one can see enough detail in the digital circuit signal, such as in millivolts or picoseconds, then all circuits are analog. This consideration is particularly important in nanometer CMOS processes, where power rail noise, jitter, temperature, and parameter variations have significant effects on 1V power rails and sub-nanosecond clock periods. BIST circuits that test analog circuits are susceptible to these effects, even if the BIST is almost entirely digital, so many analog designers want to understand how analog BIST can be more accurate than analog circuits on the same chip.

2 Challenges in Designing Analog BIST

Designing a BIST for analog circuits is more complex than accurately providing and capturing analog signals. There are many more signal variations and parameters that need to be measured than the logic 0s and logic 1s that digital BIST deals with. Analog stimuli and responses can range from DC voltages, linear ramps, and pulses to sine waves and frequency modulation. The stimuli and responses may also belong to different domains, further complicating the challenge. For example, a DC voltage input may produce a frequency output. Add to the challenge the various parameters that need to be analyzed, which may include amplitude, phase delay, and SNR (signal-to-noise ratio), as well as DC voltage, peak-to-peak jitter, and duty cycle.

Test equipment must typically be an order of magnitude more accurate than the circuit under test. The most daunting analog BIST challenge, then, is how to economically achieve higher accuracy than the circuit under test, which is likely already as accurate as it can be given its silicon area and technology. The range of signal amplitudes can be enormous. ADCs and DACs can handle on-chip analog signals with a dynamic range of up to 224, or eight orders of magnitude.

Digital BIST can be likened to a student grading his or her own multiple-choice test. He or she places a template on the answer sheet and counts the correct answers. Analog BIST, on the other hand, can be likened to a student taking an essay test. It is not a simple, objective process. Now, given the fundamental circuit principles that must be applied to practical analog BIST, the magnitude of the challenge should be apparent.

3 Basic Circuit Principles

3.1 Principle 1

The test mechanism itself must be testable by applying timing-insensitive digital test patterns, clocks, and DC voltages without the need for off-chip linear AC signals or measurements. ATE (automatic test equipment) undergoes extensive calibration and testing before leaving the factory. For BIST to be an alternative to mixed-signal ATE, it must be calibrated and tested before use. Using scan-based testing, the purely digital portion of the analog BIST circuit should be testable, including the logic BIST. If the digital circuit contains delay lines or delay matching lines, these delays and delay deltas should be tested. One way to measure a delay is to include or configure the delay line into a loop oscillator and measure its oscillation frequency with an on-chip frequency counter.

Testing the purely analog portion of analog BIST is more complex. Some researchers suggest using an ADC or DAC in their analog BIST, implicitly assuming that ATE can test it; however, mixed-signal ATE will still be necessary, thus undermining many of the advantages of BIST.

Perhaps the oldest BIST technique is to connect a DAC output back to an ADC input, or a modulator output to a demodulator input, to complete the entire digital test. This approach is like using one untested circuit to test another circuit and is insensitive to compensation errors. For example, for similar nonlinearities compensated in the ADC, the nonlinearity of the DAC may be too high because the two together are better than either alone.

3.2 Principle 2

The second principle of analog BIST is undersampling, that is, sampling slower than the Nyquist rate, which means sampling at a rate less than twice the highest frequency - this is necessary to analyze a signal more slowly. Slower sampling also helps make the BIST circuit smaller than the circuit under test.

In some self-calibration methods, a low-speed ADC is used to undersample the analog signal of a high-speed ADC or DAC. A primary sigma-delta modulator is a small, simple analog circuit that can convert an analog signal to a digital bit stream of arbitrary resolution if the bandwidth is reduced. The modulator can sample a signal 16 million times/sec, producing 1600 1-bit samples; the modulator can digitally filter these samples to produce 1 million 4-bit resolution samples/sec, or 16,000 16-bit samples/sec, in each case reducing the available bandwidth by a factor of 16. Undersampling allows a narrower bandwidth of interest to be centered on the original signal frequency, translating it to a lower frequency that is more convenient for analysis. However, undersampling comes at the expense of aliasing effects, which must be considered.

Another example of sampling is a PLL BIST that uses the PLL's input reference clock edges to sample the PLL's output (Figure 1a). In this case, a reference clocks a latch through an adjustable delay line, which performs the sampling. Suppose the latch's output counts for 1000 clock cycles and then increments the delay. This action is repeated until the latch acquires the accumulated distribution function (Figure 1b). The PLL's output frequency can be many times higher than its reference frequency. This BIST cannot detect jitter between reference clock edges, but another technique that uses a slightly offset sampling frequency can sample at all points in the output phase (Figure 2).

Figure 1. PLL BIST uses the PLL's input reference clock edge to sample the PLL's output (a). A reference clocks a latch through an adjustable delay line, which performs the sampling. The latch's output counts 1000 clock cycles and then the delay is incremented. This action is repeated until the latch obtains the cumulative distribution function (b).

These two techniques represent an important principle of time measurement: controlling the time when a signal is sampled is either a constant time offset from an adjustable delay or a constant frequency offset from an adjustable oscillator, such as a PLL. Low-jitter delay is increasingly difficult to achieve in nanometer CMOS, but low-jitter frequency offset is increasingly easy to achieve.

3.3 Principle 3

Another principle of analog BIST is to improve accuracy by subtracting systematic errors. For example, when measuring voltage, the offset voltage of any comparator or op amp must be eliminated. If these circuits have a negligible offset, the offset must be measured to verify that it is indeed negligible; otherwise, its value must be subtracted. The simpler approach is to assume that the offset is large and subtract it. When measuring delay, the delay of the test access path at the input of the circuit under test must be subtracted from the delay of the output to ensure that the delay of the access path is eliminated. ATE usually uses multiplication and subtraction to do analog self-calibration, but this operation requires too much circuitry and is not economical for BIST. When systematic errors fluctuate up and down, low-frequency effects may appear, such as offsets changing at 50 Hz or 60 Hz due to power line noise.

Accuracy can be improved by adding samples to calculate the average. Random noise in a signal or measurement circuit limits the repeatability of any signal characteristic measurement. When more samples are included in a measurement, the measurement variation and repeatability are improved. Analog measurement circuits generally achieve averaging by using low-pass filtering or by using a capacitor for charge integration.

Full adders can be used in digital circuits for analog BIST, but in many cases, averaging can be more efficiently implemented using binary counters. Non-random noise, such as interference from adjacent synchronous logic or 60 Hz power lines, cannot be suppressed by simple averaging or subtraction. However, its effects can be reduced by synchronous sampling with the interference or by integrating the interference frequency over an integer number of cycles.

To be cost-effective, the BIST circuit must have a higher yield than the circuit under test. In the case of digital BIST, this requirement simply means that its area must be smaller than the circuit under test. However, for analog BIST, this principle also means that the BIST must achieve the required linearity, noise, and bandwidth without affecting the yield. In one study, only 70% of the small analog BIST circuits on a test chip could achieve the required measurement accuracy. The yield impact of this BIST on the SoC (system on chip) is equivalent to the case where the circuit accounts for 30% of the entire SoC.

The best way to get a higher yield from BIST than the analog circuits being tested is to minimize the amount of analog circuitry in the BIST, i.e., to digitize it. By sharing a BIST circuit between multiple functions, the area associated with the BIST circuit can be reduced. Digital BIST can easily accomplish this task, but analog BIST is not as easy to do because of the diversity between the functions that need to be tested. This is where MadBIST was created, a method developed by MF Toner and Gordon W Roberts. With MadBIST, a DSP first tests an ADC and then the DAC. MadBIST, ADC and DAC, then other analog circuits.

One problem with using a shared analysis block is getting the analog signal of interest to the analysis block. This is typically done using analog buses, but they introduce loading, noise, and nonlinearity, and reduce bandwidth. An alternative approach is to convert the signal locally to some digital representation and then use a digital bus.

Analog BIST must be able to employ specification-based structured testing. In other words, the results of the stimulus and response analysis must be able to be verified against the functional specifications of the analog circuits, but they must also be oriented toward manufacturing defects to aid in diagnosis and minimize test time. Defect-oriented testing helps accomplish this task, but it is not generally attempted to use emulated functional testing. Philips (now NXP) first made a public industry comparison between traditional specification-based analog testing and defect-oriented testing in 1995. The conclusion was that defect-oriented testing can achieve faster testing for similar defect coverage when the design specifications have greater margins and the process is well controlled. On the other hand, specification-based testing is necessary to maintain test coverage and yield.

Digital BIST naturally uses a pseudo-functional stimulus because almost any pattern of 1s and 0s can represent the input signal in functional mode, including pseudo-random data. Providing a pseudo-functional stimulus for analog circuits can be much more complicated. Pseudo-random noise is an attractive analog stimulus that can handle many potential defects and is easy to generate. A resistor and a capacitor can filter the output of the LFSR in digital BIST to produce an analog waveform. Multipliers and adders can cross-correlate the response of the analog circuit under test with its pseudo-random input.

Another, more easily implemented approach is to reconfigure the circuit as an oscillator by connecting the circuit output to the input, adding gain or inversion as necessary, and measuring its oscillation frequency. This technique is area efficient. Unfortunately, both approaches have proven difficult to use because the measurements are too insensitive to noise and nonlinearity, and the diagnostics are not practical.

ATE widely uses a linear ramp and single-tone sine wave as test stimulus to effectively test the linearity of ADCs and DACs and as a diagnostic aid. The most powerful way to generate a pure ramp or sine wave on-chip is to store a periodic sigma-delta bit stream in a circular shift register, but this solution may require thousands of logic gates, plus analog filtering. Fortunately, a single stimulus block may be sufficient to handle all analog functions in an SoC and can effectively send a serial digital bit stream to various areas of the chip.

The simplest useful signal for stimulus generation is a digital square wave, which can be used to measure a step size, or an impulse response. Surprisingly, an accurate DC voltage is a difficult stimulus or reference for a sampling comparator used to generate the waveform, unless one resorts to analog techniques that require more self-testing. Low-pass filtering a digital waveform with a programmable duty cycle can produce a waveform that is essentially DC, with an average voltage that depends on the duty cycle, and reducing the switching frequency at high switching reduces the sensitivity of the DC voltage to this mismatch, but increases the peak-to-peak variation of the DC voltage. In analog functions such as regulators, the addition of active low-pass filtering can reduce this noise. But analog BIST using this approach must test the filtering. More suitable for BIST is a technique just demonstrated at the "High-Speed ​​Analog Circuit Test and Verification Workshop."

3.4 Principle 4

The final principle of analog BIST is that the result must be output as a digital measurement and pass/fail bit by comparing to upper and lower test limits. If an analog voltage result is sent off-chip for characterization, it may be corrupted and may require mixed-signal ATE. A digital result that is not compared to the limits on-chip may require ATE to capture and analyze digital words rather than individual bits, which precludes the use of the most common test pattern languages ​​WGL (waveform generation language) and STIL (standard test interface language), as well as many low-cost testers. Pass/fail results alone will not determine parameter characteristics and lack measurement repeatability, which is a fundamental step in setting test limits.

With these basic principles in mind, practical PLL BIST uses neither analog circuits nor delay lines, so it is less sensitive to noise than the PLL under test. For example, the PLL must generate a low-jitter edge every nanosecond and minimize jitter accumulation. However, PLL BIST can undersample the edges with a pretested low-jitter clock that is routed through several digital inverters that have fast switching performance to minimize additive jitter.

If there is no pre-tested clock, the PLL may sample the edges of another PLL on the same chip that operates at a slightly asynchronous frequency. The resulting jitter measurement is the sum of the two jitter levels; random jitter is unlikely to cancel each other out. Adding many such samples to a histogram can reduce the effect of spurious noise, and sampling at the same rate as any interferers can further reduce this effect.

4 Requirements for Analog BIST

Few analog BIST techniques have been proposed in the past 15 years that incorporate all of the above principles. Yet all of these principles are key to making BIST practical and cost-effective. Developing a practical analog BIST has proven too challenging, but engineers will undoubtedly develop techniques that incorporate these principles as the need for them continues to increase.

More system analog functions are being added to SoCs, with more pin counts and gate counts, all of which drive up test time and test costs. Adding embedded flash memory will greatly increase test time (far more than a minute), making multi-address testing a must, which in turn drives the need for low pin access and more analog test resources.