RF power MOSFET products and process development

Introduction

The largest application of RF power MOSFET is RF power amplifier in wireless communication. Until the mid-1990s, RF power MOSFETs used silicon bipolar transistors or GaAs MOSFETs. By the late 1990s, the emergence of the Internet had changed this situation. Compared with silicon bipolar transistors or GaAs MOSFETs, silicon-based LDMOSFETs have the advantages of small distortion, good linearity, and low cost, and have become the mainstream technology of RF power MOSFETs.
The output power of power amplifiers in mobile phone base stations ranges from 5W to more than 250W, and RF power MOSFETs are the most expensive components in mobile phone base stations. The cost of the RF part of a typical mobile phone base station is about US$65,000, of which the cost of the power amplifier reaches US$40,000. Annual sales of power amplifier components are approximately $800 million. With the development of 3G, the demand for RF power amplifiers will further increase.

RF power MOSFET is also used in the field of radio communications. Its frequency has been extended to the low microwave band and the output power can reach more than 100W. It is also used in television (especially digital television) power amplifiers, radar systems and military communications.

With the rapid development and increasingly widespread application of new generation wireless communication technology, RF power MOSFET has a very optimistic market prospect. At present, the RF power devices used in China still rely on imports, and domestic RF chips and devices account for less than 1% of their own products. Therefore, independent development of RF power MOSFETs is of great significance.

Figure 1 Basic structure diagram of LDMOSFET

Performance characteristics of RF power LDMOSFET

Compared with silicon bipolar transistors, RF power LDMOSFET has the following advantages:

1. Higher operating frequency and good stability: bipolar transistors can only operate in the frequency band below 300MHz, while LDMOSFETs have the following advantages due to feedback capacitance It is small, can work at frequencies from hundreds of MHz to several GHz, and has good frequency stability.
2. High gain: Usually at the same output power level, the gain of bipolar transistors is 8dB~9dB, while LDMOSFET can reach 14dB.
3. Good linearity and low distortion: Especially in digital signal transmission applications, LDMOSFET performs more prominently.
4. Good thermal stability: Temperature has a negative feedback effect on the LDMOSFET current, and an increase in temperature can limit the further increase of the current; while the temperature of a bipolar transistor has a positive feedback effect on the current, so the LDMOSFET has good thermal stability.

Basic structure and manufacturing process characteristics of RF power LDMOSFET

RF power LDMOSFET is a power MOSFET with a lateral channel structure. It uses LDMOSFET as the basic structure and uses double diffusion technology to sequentially diffuse boron and phosphorus twice in the same window. The difference in diffusion junction depth precisely controls the channel length. Its basic structure is shown in Figure 1 and consists of several key structures:

1. P+ substrate and P- epitaxial layer: Devices generally use P+ silicon substrate plus a certain thickness of P- epitaxial layer. The purpose of using P+ substrate is to The source end can be well extracted from the back; the P-epitaxial layer is to increase the source-drain breakdown voltage of the device.
2. P-well, N+ source/drain, gate oxide and polycrystalline gate: These are the basic elements that make up the MOS structure. The P-well and N+ source are formed through self-aligned implantation and double diffusion technology. After the P-well and N+ source are implanted, they diffuse laterally under the polycrystal, and finally form the channel and source region of the MOS.
3. LDD structure: From the edge of the polycrystalline gate to the drain end is a lightly doped LDD (Lightly Doped Drain) area. This area can withstand the high voltage between the source and drain. By optimizing the charge and length of the LDD region, the source-drain punch-through voltage can be maximized. Generally speaking, when the charge density in the LDD area is about 1011 cm-2~1013cm-2, the maximum source-drain punch-through voltage can be obtained.
4. P+ buried layer: connects the surface source terminal and the P+ substrate. During operation, the current flows from the surface source through the P+ buried layer to the P+ substrate and is drawn out from the back. This eliminates the need for additional leads from the front, reduces the feedback capacitor inductance, and improves frequency characteristics.
5. P+ enhancement area (P+ enhancement) and metal shield (shield): The P+ enhancement area is to ensure that the current flows from the source end of the surface through the metal to the P+ buried layer. The metal shielding structure is to reduce the voltage at the edge of the polycrystalline gate near the LDD area and prevent hot electron injection effects.

Product design difficulty analysis and solutions

By analyzing the performance and structural characteristics of RF power MOSFET devices, this article designs the basic structure of the device, and obtains key parameters through process and device simulation.

The key parameters of the device include:

1. Gate oxide thickness: The appropriate gate oxide thickness needs to be designed according to the threshold voltage of the device.
2. Channel length, impurity concentration and distribution: They determine the turn-on voltage of the device and the punch-through voltage between source and drain, and must be specially designed.
3. LDD length and impurity concentration: The LDD region shares the largest part of the source-drain voltage. Its length and impurity concentration distribution must be optimized so that the breakdown voltage of the device can reach the maximum value and the voltage distribution in the LDD region is uniform.
4. Epitaxial thickness and impurity concentration: They determine the vertical punch-through voltage between the N+ drain and the source derived from the substrate.
Combined with the 6-inch chip production line, the RF power MOSFET manufacturing process design is completed, including: P+ buried layer, LOCOS, gate structure, P-well, source-drain and LDD structure, as well as contact holes, aluminum, and passivation layer.

The process difficulties and solutions are as follows:

1. Gate structure: A special gate structure and process manufacturing process are designed to meet the needs of device function and frequency characteristics.
2. Self-aligned implantation and double diffusion process of P-well and N+ source regions: The device channel is formed by the difference in lateral diffusion of boron and phosphorus during the advancement of P-well and N+ source regions. These two regions are formed by two polycrystalline single-sided self-aligned implants. The injection and advancement processes need to be strictly controlled.
3. P+ well channel: The impurity concentration and length in this area are key factors that determine device performance. The injection and advancement process must be strictly controlled during the manufacturing process to ensure the basic performance and uniformity of the device.

Conclusion

This article designed the RF power LDMOSFET device structure by analyzing the performance and structural characteristics of the RF power LDMOSFET, determined the key parameters through process and device simulation, and designed a manufacturing process that is consistent with the 6-inch chip production line. Difficulties suggest solutions.

参考文献

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