Design of high-precision and high-speed A/D converter clock stabilization circuit

After entering the 21st century, human society has fully entered the information age. The information industry has become the most important pillar and main industry of modern society. With the rapid development of semiconductor technology, digital signal processing technology and communication technology, A/D, D /A converters have also shown a rapid development trend in recent years. With the development of high-speed and high-precision A/D converters (ADCs), especially the launch of high-resolution data converters that can directly perform intermediate frequency sampling, stable sampling The demand for clocks is becoming more and more urgent. As the clock speed in communication systems reaches the GHz level, phase noise and clock jitter have become factors that must be considered in analog design.

The main function of a data converter is either to generate an analog waveform from periodic time samples, or to generate a series of periodic time samples from an analog signal. Therefore, the stability of the sampling clock is very important. From a data converter's perspective, this instability (i.e., random clock jitter) creates uncertainty in when the analog-to-digital converter samples the input signal. In high-speed systems, the timing error of the clock or oscillator waveform will limit the maximum rate of a digital I/O interface. Not only that, it will also increase the bit error rate of the communication link and even limit the A/D converter. (ADC) dynamic range, in order to obtain the best performance of the data converter, it is extremely important to appropriately select the sampling encoding clock.

ADC circuit

In recent years, foreign research on high-speed A/D converters has been the most active, and some improved structures have appeared on the basic Flash structure [2], such as partitioned hierarchical (subranging) circuit structure (such as half-flash structure, Pipelined, Multistage structure, Multistep structure). In fact, they are circuit structures composed of multiple Flash circuit structures and other functional circuits in different forms. This structure can make up for the shortcomings of the basic Flash circuit structure and is an ideal way to realize high-speed and high-resolution A/D converters. Excellent circuit design technology, this structure is gradually replacing the long-established SAR and integral structures. In addition, there is a type of bit-per-stage circuit structure. Further improvements on its basis will result in a A circuit structure called Folding (also known as Mag Amps structure) is a Gray code serial output structure. These circuit design technologies are the development of high-speed, high-resolution, and high-performance A/D converters. Played a positive role in promoting.

In addition, in high-resolution A/D converter circuit design technology, Σ-Δ circuit structure is a very popular circuit design technology at present. This circuit structure is not only used in high-resolution low-speed or medium-speed A/D converters. It will gradually replace SAR and integrating circuit structures, and this structure, combined with the pipeline structure, is expected to achieve higher resolution and higher speed A/D converters.

Clock duty cycle stabilization circuit

As the functions of electronic systems in weapons and equipment continue to expand and their performance continues to improve in the new era, the complexity of electronic systems also continues to increase. In order to ensure the data sampling, control feedback and digital processing capabilities of the electronic system and Performance, modern military electronic systems have increasingly higher requirements for A/D converters, especially military data communication systems and data acquisition systems. The demand for high-speed and high-resolution A/D converters is increasing, and clocks account for As the core unit of a high-speed and high-precision A/D converter, the space ratio stabilization circuit plays a vital role in the converter's signal-to-noise ratio (SNR) and effective bit (ENOB) performance. Therefore, it is necessary to ensure high speed and high precision. The performance of the A/D converter must first ensure that the sampling encoding clock has a suitable duty cycle and small jitter. Therefore, it is very necessary to carry out research on clock duty cycle stabilization circuits.

Since the clock duty cycle stabilization circuit is the core unit of high-speed, high-precision A/D converters, and there are almost no independent clock duty cycle stabilization circuit products, it is only reported in high-speed, high-precision A/D converters. The reason why ADI's products can improve the sampling performance compared with other companies' products is mainly due to the improvement of the DCS (duty cycle stabilizer) circuit. The DCS circuit is responsible for reducing the jitter of the clock signal, and the sampling timing depends on the clock. signal, the past DCS circuits of various companies can only control the jitter to about 0.25ps, while the high-performance new products AD9446 and LTC2208 can reduce the jitter to about 50fs. Generally, reducing the jitter can improve the SNR, thereby increasing the effective resolution ( ENOB (effective number of bits), and can achieve a sampling rate of more than 100Msps while reaching 16 quantization bits. If the sampling rate is increased without controlling jitter, ENOB will be reduced, and the desired resolution cannot be obtained, and The number of quantization bits cannot be increased. With the development of high-performance A/D converters, DCS circuits can develop towards higher speed, smaller jitter and stability. Table 1 lists the clock duty of foreign A/D converters. The main technical and parameter indicators of the ratio stability circuit.

In fact, AD's 60fs jitter is already the smallest so far. Nowadays, aperture jitter is generally controlled at about 1 ps. Jitters higher than this number or even as high as dozens of ps are actually meaningless.

Implementation method of clock stabilization circuit

Judging from the current research situation at home and abroad, the clock circuit used to stabilize high-speed ADC is mainly a phase-locked loop (PLL). The phase-locked system is essentially a closed-loop phase control system. To put it simply, it is a circuit that can synchronize the output signal with the input signal in frequency and phase. That is, after the system enters the locked state (or synchronized state), The phase difference between the oscillator output signal and the input signal is zero or constant. Since the phase-locked loop has many excellent characteristics, it can be widely used in clock generation and distribution of high-performance processors, system frequency synthesis and conversion, automatic Frequency tuning tracking, bit synchronization extraction in digital communications, phase locking, phase locking frequency multiplication and frequency division, etc.

This article proposes a design scheme for a delay-locked loop (Delay-locked loop DLL). In fact, the PLL mainly uses the phase detector and filter to monitor the feedback clock signal and the input clock signal, and then uses the generated voltage difference to Control the voltage controlled oscillator to generate a signal that is similar to the input clock, and ultimately achieve the purpose of frequency locking. The function of the DLL is to insert a delay pulse between the input clock and the feedback clock until the rising edges of the two clocks are aligned, and To achieve synchronization, when the input clock pulse edge and the feedback pulse edge are aligned, the on-chip delay phase-locked loop DLL can be locked. After locking the clock, the circuit no longer adjusts, and there is no difference between the two clocks. In this way, the on-chip delay phase-locked loop uses the DLL output clock to compensate for the time delay caused by the clock distribution network, thus effectively improving the relationship between the clock source and the load. time delay between. First, a delay line is less noisy than an oscillator because the damaged zero crossings in the waveform disappear at the end of the delay line and are recycled in the oscillator circuit, thus producing more Secondly, the delay time changes rapidly within the change of the control voltage in the DLL. That is to say, the transfer function is simply equal to the gain KBCDL of VCDL. In short, the oscillator used in the PLL has instability and phase offset. Accumulation, therefore, often reduces the performance of the PLL when compensating for clock delays caused by the network respectively. Therefore, issues such as stability and stable speed of the DLL are better than that of the PLL.

◇ Overall circuit structure design

The overall structure of the clock duty cycle stabilization circuit is shown in the dotted box in Figure 1. It consists of input buffer amplifier A, switches K1, K2 and delay locked loop (DLL).

When the sampling clock frequency is lower than the lower operating limit of the DLL, the switches K1 and K2 are closed upward and the DLL is bypassed; when the switches K1 and K2 are closed downward, the DLL starts to function and adjusts the input clock signal phase so that the input clock The duty cycle is close to 50% and the jitter is less than 0.5ps.

◇ Delay-locked loop (DLL)

The structure of delay-locked loop (DLL) is similar to ordinary phase-locked loop (Phase-locked loop, PLL). It just uses voltage control delay line (VCDL, Voltage Control Delay Line) instead of a voltage controlled oscillator. The structural block diagram is shown in Figure 2. An ordinary DLL includes four main modules: phase detector, charge pump circuit, loop filter and VCDL. The voltage-controlled delay line is an open-circuit chain composed of a series of voltage-controlled delay variable power supplies connected in series, and its output signal is the delay ntd of the input signal. The input and output of the voltage-controlled delay line are sent to the phase detector for comparison, and the phase difference between the two is locked at one cycle (in-phase comparison) or half cycle (inversion comparison) through the phase-locked loop. Then each delay The delay time of the unit is T/n or T/2n, where n is the number of delays.

The function of the phase detector in the DLL is to identify the phase error and adjust the error of the charge pump to control the output frequency of the voltage oscillator. Common phase identification characteristics include cosine type, sawtooth type and triangle type. The phase detector can be divided into There are two types of phase detectors: analog phase detector and digital phase detector. Their main indicators are:

(1) Phase detection characteristic curve. That is, the output voltage of the phase detector changes with the phase difference of the input signal. This characteristic requires it to be linear and have a large linear range.

(2) Phase identification sensitivity. That is, the output voltage generated by unit phase difference, the unit is v/raJ. The phase detection sensitivity of an ideal phase detector should be independent of the amplitude of the input signal. When the phase detection characteristic is nonlinear, it is generally defined as the sensitivity at the Pt=0 point.

(3) Phase detection range, that is, the phase range in which the output voltage changes monotonically with the phase difference.

(4) Operating frequency of the phase detector.

The charge pump in the DLL is actually a charge switch, which allows the phase difference and lead and lag to be converted into current, and then converted into a control voltage through the integral action of the first-order capacitor, and then use this feedback control voltage to control the delay time. to achieve the required phase delay.

The DLL has two functions: one is to detect the duty cycle; the other is to detect clock jitter. Since the delay lock is 50% of the clock cycle, when the phase detector (PDF) detects that the duty cycle is greater than 50%, the charge When the pump (CP) moves upward, the duty cycle decreases, and when the pump (CP) moves downward, the duty cycle increases.