Explore new microelectronic packaging technology

1 Introduction

This paper attempts to review the new microelectronic packaging technologies that have developed rapidly since the 1990s, including ball grid array packaging (BGA), chip size packaging (CSP), wafer level packaging (WLP), three-dimensional packaging (3D) and system in package (SIP). It introduces their development status and technical characteristics. At the same time, it describes the concept of microelectronic three-level packaging. And puts forward some thoughts and suggestions on the development of new microelectronic packaging technologies in my country.

2 Microelectronics tertiary packaging

Microelectronic packaging, first we need to describe the concept of three-level packaging. Generally speaking, microelectronic packaging is divided into three levels. The so-called first-level packaging is to package one or more integrated circuit chips in a suitable packaging form after the semiconductor wafer is split, and the chip's soldering area is connected to the external pins of the package by wire bonding (WB), tape automated bonding (TAB) and flip chip bonding (FCB), so that it becomes an electronic component or assembly with practical functions. The first-level packaging includes two categories: single chip module (SCM) and multi-chip module (MCM). It should be said that the first-level packaging includes the entire process from wafer splitting to circuit testing, which is what we often call back-end packaging, and also includes the design and production of single chip modules (SCM) and multi-chip modules (MCM), as well as various packaging materials such as wire bonding wires, lead frames, chip mounting glue and epoxy molding compounds. This level is also called chip-level packaging. The second-level packaging is to install the first-level microelectronic package products together with passive components on a printed circuit board or other substrate to become a component or a complete machine. The installation technologies used at this level include through-hole mounting technology (THT), surface mounting technology (SMT) and direct chip mounting technology (DCA). The second-level packaging should also include the materials, design and manufacturing technologies of double-layer and multi-layer printed circuit boards, flexible circuit boards and various substrates. This level is also called board-level packaging. The third-level packaging is to connect the second-level packaged products with the motherboard through layer selection, interconnection sockets or flexible circuit boards to form a three-dimensional package to form a complete whole machine system. This level of packaging should include connectors, stacked assembly and flexible circuit boards and other related materials, design and assembly technologies. This level is also called system-level packaging. The so-called microelectronic packaging is an overall concept, including all technical contents from single-pole packaging to three-pole packaging. Internationally, microelectronic packaging is a very broad concept, including many contents of assembly and packaging. The scope of microelectronic packaging should include single chip packaging (SCP) design and manufacturing, multi-chip packaging (MCM) design and manufacturing, chip post-packaging process, various packaging substrate design and manufacturing, chip interconnection and assembly, overall electrical performance, mechanical performance, thermal performance and reliability design of packaging, packaging materials, packaging molds and fixtures, and green packaging. Some people say that microelectronic packaging is just a packaging shell; others say that microelectronic packaging is just a passive component and cannot be active; others say that microelectronic packaging is just an enclosure and is dispensable, etc. These views are one-sided and incorrect. We should incorporate the existing understanding into the track of international microelectronic packaging, which will not only benefit the technical exchanges between my country's microelectronic packaging industry and foreign countries, but also benefit the development of my country's microelectronic packaging itself.

3 New microelectronic packaging technology

The history of integrated circuit packaging can be divided into three stages. The first stage, before the 1970s, was dominated by plug-in packaging. Including the initial metal round (TO-type) package, and later ceramic dual in-line package (CDIP), ceramic-glass dual in-line package (CerDIP) and plastic dual in-line package (PDIP). In particular, PDIP has become a mainstream product due to its excellent performance, low cost and mass production. The second stage, after the 1980s, was dominated by surface-mounted quad-lead packages. At that time, surface mounting technology was called a revolution in the field of electronic packaging and developed rapidly. In line with this, a number of packaging forms adapted to surface mounting technology, such as plastic leaded chip cutouts (PLCC), plastic quad flat packages (PQFP), plastic small outline packages (PSOP) and leadless quad flat packages, came into being and developed rapidly. Due to its high density, small lead pitch, low cost and suitability for surface mounting, PQFP became the dominant product of this period. The third stage, after the 1990s, was dominated by surface array packaging. In the early 1990s, integrated circuits developed to the ultra-large-scale stage, requiring integrated circuit packaging to develop towards higher density and higher speed. Therefore, integrated circuit packaging developed from four-sided lead type to planar array type, and the ball array package (BGA) was invented, which soon became the mainstream product. Later, various CSPs with smaller packaging volumes were developed. In the same period, multi-chip modules (MCMs) flourished, also known as a revolution in electronic packaging. Due to different substrate materials, they are divided into multilayer ceramic substrate MCM (MCM-C). Thin film multilayer substrate MCM (MCM-D), plastic multilayer printed circuit board MCM (MCM-L) and thick film substrate MCM (MCM-C/D). At the same time, due to the needs of circuit density and function, 3D packaging and system packaging (SIP) have also developed rapidly. This article calls the packaging developed since the 1990s a new type of microelectronic packaging. The following describes BGA, CSP, 3D and SIP respectively.

3.1 Ball Array Package (BGA)

Block Grid Array (BGA) is a new type of package developed in the early 1990s in the world.

The outstanding advantages of this BGA are: ① Better electrical performance: BGA uses solder balls instead of leads, and the lead-out path is short, which reduces pin delay, resistance, capacitance and inductance; ② Higher packaging density; Since the solder balls are arranged in the entire plane, the number of pins is higher for the same area. For example, a BGA with a side length of 31mm has 900 pins when the solder ball pitch is 1mm. In contrast, a QFP with a side length of 32mm and a pin pitch of 0.5mm has only 208 pins; ③ The pitch of BGA is 1.5mm, 1.27mm, 1.0mm, 0.8mm, 0.65mm and 0.5mm, which is fully compatible with existing surface mounting processes and equipment, and the installation is more reliable; ④ Due to the "self-alignment" effect of the surface tension when the solder melts, the loss of deformation of the traditional package leads is avoided, greatly improving the assembly yield; ⑤ BGA pins are firm and easy to transport; ⑥ The solder ball lead-out form is also suitable for multi-chip components and system packaging. Therefore, BGA has developed explosively. BGA has plastic ball array package (PBGA), ceramic ball array package (CBGA), tape ball array package (TBGA), heat sink ball array package (EBGA), metal ball array package (MBGA), and flip chip ball array package (FCBGA) due to different substrate materials. PQFP can be applied to surface mounting, which is its main advantage. However, when the lead pitch of PQFP reaches 0.5mm, the complexity of its assembly technology will increase. Therefore, PQFP is generally used for lower lead counts (208) and smaller package sizes ( 28mm square). Therefore, in applications where the number of leads is greater than 200 and the package size is greater than 28mm square, it is inevitable that BGA package will replace PQFP. Among the above types of BGA packages, FCBGA is most likely to become the fastest growing BGA package. Let's take it as an example to describe the process technology and materials of BGA. In addition to all the advantages of BGA, FCBGA also has the following advantages: ① Excellent thermal performance, a heat sink can be installed on the back of the chip; ② High reliability, due to the effect of the filler under the chip, the fatigue life of FCBGA is greatly enhanced; ③ Strong reworkability.

The key technologies involved in FCBGA include chip bump production technology, flip chip welding technology, multi-layer printed circuit board production technology (including multi-layer ceramic substrate and BT resin substrate), chip bottom filling technology, solder ball attachment technology, heat sink attachment technology, etc. The packaging materials involved mainly include the following categories. Bump materials: Au, PbSn and AuSn, etc.; Under-bump metallization materials: Al/Niv/Cu, Ti/Ni/Cu or Ti/W/Au; Soldering materials: PbSn solder, lead-free solder; Multi-layer substrate materials: high-temperature co-fired ceramic substrate (HTCC), low-temperature co-fired ceramic substrate (LTCC), BT resin substrate; Bottom filling material: liquid resin; Thermal conductive adhesive: silicone resin; Heat sink: copper. At present, the typical series of FCBGA in the world are shown in Table 1.

3.2 Chip Scale Package (CSP)

Chip size package (CSP) and BGA are products of the same era, and are the result of miniaturization and portability of the whole machine. The definition of CSP given by JEDEC in the United States is: the package with an LSI chip package area less than or equal to 120% of the LSI chip area is called CSP. Since many CSPs adopt the form of BGA, in the past two years, authoritative figures in the packaging industry believe that the solder ball pitch is greater than or equal to 1mm for BGA, and less than 1mm for CSP. Because CSP has more outstanding advantages: ① ultra-small package similar to chip size; ② protect bare chips; ③ excellent electrical and thermal properties; ④ high packaging density; ⑤ easy to test and aging; ⑥ easy to weld, install, and repair and replace. Therefore, it has developed rapidly in the mid-1990s, doubling its growth every year. Since CSP is in a booming stage, its types are limited. Such as rigid substrate CSP, flexible substrate CSP, lead frame CSP, micro molded CSP, pad array CSP, micro BGA, bump chip carrier (BCC), QFN CSP, chip stacking CSP and wafer level CSP (WLCSP). The lead pitch of CSP is generally below 1.0mm, including 1.0mm, 0.8mm, 0.65mm, 0.5mm, 0.4mm, 0.3mm and 0.25mm. Table 2 shows the CSP series.

Generally, CSP is to cut the wafer into individual IC chips before implementing the back-end packaging. However, WLCSP is different. All or most of its process steps are completed on the silicon wafer that has completed the previous process, and finally the wafer is directly cut into separate independent devices. Therefore, this kind of packaging is also called wafer-level packaging (WLP). Therefore, in addition to the common advantages of CSP, it also has unique advantages: ① High packaging processing efficiency, multiple wafers can be processed at the same time; ② It has the advantages of flip chip packaging, that is, light, thin, short and small; ③ Compared with the previous process, only two processes of pin rewiring (RDL) and bump production are added, and the rest are all traditional processes; ④ Reduce the multiple tests in traditional packaging. Therefore, major IC packaging companies in the world have invested in the research, development and production of this type of WLCSP. The disadvantages of WLCSP are that the number of pins is currently low, it has not been standardized and the cost is high. Figure 4 shows the appearance of WLCSP. Figure 5 shows the process flow of this WLCSP.

In addition to the metal deposition technology, photolithography technology, etching technology, etc. required for the previous process, the key technologies involved in WLCSP also include rewiring (RDL) technology and bump production technology. Usually, the lead pads on the chip are arranged in a square aluminum layer around the die. In order to adapt WLP to the wider pad pitch of the SMT secondary package, these pads need to be redistributed, so that these pads are arranged on the chip active surface instead of the chip periphery. This requires rewiring (RDL) technology. In addition, the square aluminum pad is changed to a circular copper pad that is easy to bond with solder. The sputtered under-bump metal (UBM) in the rewiring, such as Cu in Ti-Cu-Ni, should have sufficient thickness (such as hundreds of microns) so that the solder bump has sufficient strength when connected. The Cu layer can also be thickened by electroplating. Solder bump production technology can be achieved by electroplating, chemical plating, evaporation, ball placement and solder paste printing. At present, electroplating is still the most widely used, followed by solder paste printing. The UBM materials in the rewiring are Al/Niv/Cu, T1/Cu/Ni or Ti/W/Au. The dielectric materials used are photosensitive BCB (benzocyclobutene) or PI (polyimide). The bump materials are Au, PbSn, AuSn, In, etc.