What is a tri-state gate? Tri-state logic and NAND gate circuit and tri-state gate circuit

A three-state gate is a logic gate whose output has a third state in addition to the two states of high and low levels - a high-impedance state. The high-impedance state is equivalent to the isolation state. All three-state gates have an EN control enable terminal to control the on and off of the gate circuit. Devices that can have these three states are called three-state (gates, buses, etc.).
For example:
a storage unit in the memory, when the read-write control line is at a low potential, the storage unit is opened and can be written into it; when it is at a high potential, it can be read, but it is not read or written, so it must use a high resistance state, which is neither +5v nor 0v.
Computers use 1 and 0 to represent two logics, yes and no, but sometimes, this is not enough.
For example, he is not rich enough, but he is not necessarily poor. She is not beautiful, but she is not necessarily ugly.
In the middle of these two extremes, it is represented by the intermediate state that is neither + nor -, which is called a high-impedance state.
High and low levels can be pulled up and down by internal circuits. In high impedance state, the resistance of the pin to ground is infinite, and the real level value can be read when reading the pin level.
The important role of high impedance state is to read the external level of the I/O (input/output) port during input.

1. Features of three-state gate

The three-state output gate is also called a three-state circuit. It is different from the general gate circuit. In addition to high level and low level, its output terminal can also appear in a third state, that is, high impedance state, also known as forbidden state, but it is not a three-logic value circuit. 2.

Three-state logic NAND gate The three-state logic NAND gate

is shown in Figure Z1123. This circuit is actually composed of two NAND gates plus a diode D2 . The right half of the dotted line is a NAND gate with an active discharge circuit, which is called the data transmission part, and uI1 and uI2 of the T5 tube are called data input terminals. The left half of the dotted line is the state control part, which is a NOT gate, and its input terminal C is called the control terminal, or the permission input terminal, or the enable terminal.

When the C terminal is connected to a low level, T4 outputs a high level to T5 , making the right half of the dotted line in working state. In this way, the circuit will transmit the signal received by uI1 and uI2 to the output terminal according to the NAND relationship , making uO either high or low . When the C terminal is connected to a high level, T4 outputs a low level to T5 , making T6 , T7 , and T10 cut off. On the other hand, the base potential of T8 is clamped at about 1V through D2 , making T9 cut off . Since T9 and T10 are both cut off, the circuit is in a high impedance state when viewed from the output terminal u0. The logic symbol of the three - state logic NAND gate is shown in Figure Z1124. Among them , Figure (a ) indicates that the C terminal is in working state when it is at a high level, which is called a high-effective three-state NAND gate. Figure (b) indicates the working state when the C terminal is at a low level, which is called a low-effective three-state NAND gate. Be careful to distinguish when using.

The most important use of the tri-state NAND gate is to transmit several different sets of data and control signals to a wire in turn, as shown in Figure Z1125. This method is widely used in computers. However, it should be pointed out that in order to ensure that many tri-state gates connected to the same bus can work properly, a necessary condition is that at most only one gate is in working state at any time, otherwise it is possible that several gates are in working state at the same time, causing abnormal output state.

Three-state output gate circuit ( TS ( Three-state output Gate ) gate)

The figure above is the schematic diagram of the tri-state gate output gate circuit. In the figure, if the two inverters and a diode in the dotted box are cut off, the remaining part is a typical TTL NAND gate circuit .

The so-called three-state refers to the output end . The _two transistors T4 and T5 at the output of the ordinary TTL NAND gate always maintain a push-pull state with one _{transistor turned on} and the other turned off. When T4 _is turned on and T5 is turned off, the output is a high level Y=1 _; when _T4 is turned off and T5 is turned on, the output is a low level, Y =0 . In addition to the above two states, the three- _state gate has a third state in which T4 and T5 are turned off at the same time. Because there is infinite impedance between c and e _when the _transistor is turned off, the output terminal Y has infinite impedance to the ground and the power supply ( _vcc ) . Therefore, this third state is also called the high-impedance state.

Now we analyze three states:

The control signal can be added at E _N or at :

E _N = 0 , = 1 , then C=0 , v _B1 =0.9V , v _c2 = 0.9V

v _B4 = v _c2 = 0.9V , T ₄ is cut off ( the potential v _B4 when T ₄ is turned on is >1.4V )

v _B1 =0.9V , T5 _is cut off, and the output terminal Y is in high impedance state.

EN = 1 , = 0 , C = 1 , which has no effect on the other two input terminals A and B of the NAND gate. _It is a normal NAND gate circuit.

When A = B = 1 , T2 _and T5 are turned on, vc2 ₌ 1.0V (analyzed before). Diode D is in the reverse cut-off state (because its anode voltage vc2 = _1.0V , which is less than the cathode point C potential vIH ₌ 3.4V ) , _and does not work in the circuit .

If _one of A and B is 0 , T2 and T5 _are cut off. Since vc2 = _vIH + 0.7 = 4.1V , it is sufficient to ensure that _T4 is _turned on.

That is , when EN = ₁ ( EN = 0 ), diode D does not work in the circuit and the circuit maintains the complete NAND gate logic function.

The logic symbol of the three-state gate is as follows:

EN = 1 , = 0 , _​

EN = 0 , Y is in high impedance state = 1 _, Y is in high impedance state

Common logic gate circuit symbols:

AND gate NAND gate NOT gate (inverter)

OR gate NOR gate AND-OR gate

Y=

OC NAND gate Tristate NAND gate

(External collector voltage C = 1 , = 0 ,

After resistance ) C=0 , high resistance = 1 , high resistance

C=1 , Y=A = 0 , Y=A

C=0 , Y high impedance = 1 , Y high impedance

C=1 , = 0 ,

C=0 , Y high impedance = 1 , Y high impedance

Example 1 : Determine the output Yi of each of the following _TTL gate circuits ( i =1, ... 16 )

Determine the value of Y ₁₆ in the table on the left . Can the three control variables A, B, and C take the four combinations of 000, 001, 010, and 100?

Example 2 : Try to draw the waveforms of Y ₁ , Y ₂ , Y ₃ , and Y _4. The waveforms of A and B are shown in the figure below:

Please draw the waveforms of Y ₃ and Y ₄ by yourself . This should be completed within half a minute (30 seconds).

Tri-state gate circuit