PCM encoding and decoding module principle

PCM encoding and decoding module principle

The principle block diagram of this module is shown in Figure 5-2. The module uses +5V and -5V voltages internally, where the -5V voltage is obtained by converting the -12V power supply through 7905.

Figure 5-2 PCM encoding and decoding Principle block diagram
The module has the following test points and input points:
• BS PCM base group clock signal (bit synchronization signal) test point
• SL0 PCM base group 0th time slot synchronization signal
• SLA signal A sampling signal and time slot synchronization signal test point
• SLB signal B sampling signal and time slot synchronization signal test point
• SRB signal B decoding output signal test point
• STA signal input to encoder A test point
• SRA signal A decoding output signal test point
• STB signal input to encoder B test point
• PCM PCM base group signal test point
• PCM-A signal A encoding result test point
• PCM-B signal B encoding result test point
• STA-IN external audio signal A input point
• STB-IN external audio signal B input point

There are three switches K5, K6 and K8 on this module. K5 and K6 are used to select the input signals of the two encoders. When the switch handle is on the left (STA-IN, STB-IN), the external signal is selected, and when it is on the right (STA-S, STB-S), the internal audio sine signal of the module is selected. K8 is used to select the SLB signal as one of the time slot synchronization signals SL1, SL2, SL5, and SL7.
The crystal oscillator, frequency divider 1, frequency divider 2 and sampling signal (time slot synchronization signal) generator constitute a timer, which provides a 2.048MHz clock signal and an 8KHz time slot synchronization signal for the two PCM encoders and decoders. In the actual communication system, the clock signal (i.e., bit synchronization signal) and time slot synchronization signal (i.e., frame synchronization signal) of the decoder should be extracted from the received data stream. Here, the clock signal and time slot synchronization signal generated by the synchronizer are directly sent to the decoder .
Since the clock frequency is 2.048MHz and the sampling signal frequency is 8KHz, the code rates of PCM-A and PCM-B are both 2Mb. There are 32 time slots in a frame, of which 1 time slot is PCM coded data and the other 31 time slots are empty time slots. The
code rate of each PCM signal is 64kb/s. 29 of the 32 time slots in a frame are empty time slots. The 0th time slot is the frame synchronization code (×1110010) time slot, the 2nd time slot is the time slot of signal A, and the 1st (or 5th, or 7th - controlled by switch K8) time slot is the time slot of signal B.
The PCM signal generated in this experiment is similar to the PCM primary group signal, but there is no signaling signal in the 16th time slot, and the signal in the 0th time slot is not exactly the same as the signal in the 0th time slot of the PCM primary group.
Since the two PCM encoders use the same clock signal, they can be synchronously multiplexed (that is, no code rate adjustment is required). Since the output data of the two encoders are in different time slots, PCM-A and PCM-B can be wired ORed. In this module, the OR gate 74LS32 is used to multiplex PCM-A, PCM-B and frame synchronization signals. Before decoding, there is no need to tap the PCM. The time slot synchronization signal of the decoder actually plays the role of signal branching.