Programmable logic devices and their applications

Programmable logic devices and applications
10.1 Overview
10.1.1 Basic structure of PLD devices
10.1.2 Classification of PLD devices
10.1.3 Advantages of PLD devices
1. Shorten design cycle and reduce design risk
2. High reliability and encryption
3. Reduce the total cost of product production

10.2 Programmable Array Logic (PAL)

10.3 General Array Logic GAL
10.3.1 Structural features of GAL
10.3.2 Structure and output configuration of output logic macrocell (OLMC)
10.3.3 GAL address allocation and programming
Homework: P333 10.1 10.3

Chapter 10 Programmable Logic Devices and Applications
10.1 Overview
10.1.1 Basic Structure of PLD Devices
The basic structure of a programmable logic device (PLD) is composed of an AND array and an OR array, plus an input buffer circuit and an output circuit. The input buffer circuit can generate the original variable and the inverse variable of the input variable and provide sufficient driving capability.

10.1.2 Classification of PLD devices
Using digital circuit network course PowerPoint

PROM, PAL and GAL only have one array that can be programmed, which is a half-field programmable logic device, while PLA's AND array and OR array are both programmable, which is a full-field programmable logic device.
GAL replaces the fixed output circuit with the output logic macrocell (OLMC), which is easy to use, flexible and widely used.

10.1.3 Advantages of PLD devices
1. Shorten the design cycle and reduce design risks
2. High reliability and encryption

3. Reduce the total cost of product production

10.2 Programmable Array Logic PAL (Taught by Digital Circuit Network Course PowerPoint)
PAL devices are classified according to the structure of their output circuits. There are four commonly used forms:
1. Dedicated output structure or array is fixed
When the output of the OR gate is connected to a common buffer, the output function is high level valid (such as: PAL10H8), if it is connected to an inverting buffer, the output function is low level valid (such as PAL10L8).
2. Asynchronous I/O output structure
Its output circuit consists of a tri-state gate and a complementary feedback buffer
3. Register output structure
It connects a synchronous D latch after the OR gate output, and the latch Q end is output through the tri-state gate
4. XOR-register output structure
Figure 10.2.5 shows the logic diagram of an XOR register output circuit. It divides a group of AND gates into the sum of two product terms, sends them to the D latch after the XOR gate, and then outputs them through the tri-state gate . At the same time, it is fed back to the AND array through the feedback buffer from the end. This structure is suitable for realizing counters and states.

10.3 General Array Logic GAL
10.3.1 Structural Features of GAL
The difference between GAL and PAL:
① PAL is a PROM fuse process and is a one-time programming device, while GAL is a process and can be repeatedly programmed;
② The output of PAL is fixed, while GAL uses a programmable output logic macrocell (OLMC) as the output circuit.
GAL is more flexible, more powerful, and more convenient to use than PAL, and can almost replace all PAL devices.
10.3.2 Structure and output configuration of output logic macrocell (OLMC)
(using digital circuit network course PowerPoint teaching)
Figure 10.3.2 is a logic diagram of an output logic macrocell of GAL.
(n) in Figure 10.3.2 represents the number of OLMC (output pin number).

1. Structure control word register
Figure 10.3.3 shows the structure control word register for OLMC programming. It has 82 bits, 32 bits at each end for product term invalidation bits, and 18 bits in the middle for control words, of which SYN and AC0 each occupy one bit, and control 8 OLMCs at the same time. AC1(n) and XOR(n) each have 8 bits, and control 8 OLMCs respectively.

SYN: It determines whether OLMC is a sequential logic circuit (D flip-flop works) or a combinational logic circuit (D flip-flop does not work). When SYN=0, OLMC is a sequential logic circuit. At this time, the D flip-flop in OLMC is in a working state and can be used to form a sequential circuit; when SYN=1, the D flip-flop in OLMC is in a non-working state, so OLMC can only be a combinational logic circuit. It should be pointed out here that when SYN=0, all 8 OLMCs can form a sequential circuit, but it does not mean that all 8 OLMCs must form a sequential circuit. Other control words can be used to make the D flip-flop not be used, so that a combinational logic output can be formed. However, as long as one OLMC needs to form a sequential logic circuit, SYN=0 must be set.
AC0, AC1 (n): Cooperate with SYN to control the output configuration of the output logic macro unit.

2. Five output configurations of OLMC

10.3.3 GAL row address allocation and programming
It is not the spatial distribution diagram of the programming unit of the actual device, so it is called an address map.

5. Line 60 is an 82-bit structure control word, which is used to set the configuration of OLMC and prohibit the 64 product terms. 6. Line 61 has only one bit, which is the encryption unit. After programming this unit, the programming array cannot be modified or read out, so the design results are kept confidential and prevented from being copied. The encryption can only be released when the chip is erased as a whole.
7. Line 63 has only one bit, which is the chip erase bit. It can restore the chip to its original state before programming.