Design of Micro-Accelerometer Data Acquisition System Based on ARM and FPGA

0 Introduction
Accelerometer is a widely used inertial sensor, which can be used to measure the acceleration of the motion system. Most of the current accelerometers are designed and manufactured using micro-electromechanical technology (MEMS). Due to the use of micro-electromechanical technology, the design size is greatly reduced. A MEMS accelerometer is only a small part of the fingernail. MEMS accelerometer has the advantages of small size, light weight, and low energy consumption.
With the increasing application of micro-accelerometers, data signal acquisition and storage of micro-accelerometers have become extremely important. Most traditional data acquisition methods are completed by single-chip microcomputers, which are simple to program and flexible to control, but the disadvantages are long control cycles and slow speeds. Especially for high-speed conversion data, the slow speed of single-chip microcomputers greatly limits the data transmission speed. FPGA (field programmable gate array) has advantages that single-chip microcomputers cannot match. FPGA has a high clock frequency, small internal delay, and all control logic is completed by hardware. It is fast and efficient, and is suitable for high-speed transmission control of large amounts of data. In terms of high-speed data acquisition, FPGA has unparalleled advantages over single-chip microcomputers. However, single-chip microcomputers have rich interfaces and strong data processing capabilities, which facilitate the display and storage of data.
Combining the advantages of single-chip microcomputers and FPGAs, this paper introduces a micro-accelerometer data acquisition and storage system based on ARM and FPGA, which combines the MXR6150G/M accelerometer sensor and TLC0820-A/D conversion chip to provide a data acquisition solution with flexible configuration and strong versatility.

1 Overall system design scheme
Figure 1 is the overall structural block diagram of the data acquisition system, which is mainly composed of four parts: dual-axis accelerometer, A/D converter, FPGA and ARM processor. The dual-axis accelerometer outputs two analog signals, representing the acceleration values ​​of the z-axis and y-axis respectively. The two analog signals are converted into 8-bit digital signals through the A/D conversion chip. The FPGA receives the digital signal from the A/D conversion chip and processes the digital signal. The processed data is cached by the FIFO memory in the FPGA and then received and collected by the ARM processor in an interrupt mode. The collected data can be displayed in real time on the PC through serial communication, or stored in a large-capacity hard disk through the IDE interface.

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2 System Hardware Design and Implementation
2.1 MXR6150G/M Accelerometer Sensor
MXR6150G/M is a dual-axis accelerometer sensor produced by Wuxi Meixin Semiconductor Co., Ltd. It is manufactured using standard submicron CMOS technology and can measure acceleration signals in the range of -5g to +5g (g is the acceleration of gravity). The accelerometer uses two analog voltages to reflect the magnitude of the acceleration value. When the accelerometer is stationary and the acceleration value is 0, the output voltage is 1.50 V, and the voltage output sensitivity is 150 mV/g. Figure 2 is a top view of the appearance of this accelerometer, and Table 1 is the pin description of the accelerometer, where pin 7 and pin 6 output the acceleration components of the x-axis and y-axis respectively. The actual acceleration value needs to be synthesized by synthesizing the acceleration values ​​of the x-axis and y-axis, which can be completed using the parallel computing processing of FPGA.

2.2 8-bit A/D conversion chip TLC0820
TLC0820 is an A/D converter manufactured by Texas Instruments (TI) using advanced LinCMOS technology. It consists of two 4-bit flash converters, a 4-bit digital/analog converter, a calculation error amplifier, control logic circuit and result latch circuit. It uses 8-bit parallel output and does not require external clock and oscillation components. It is widely used in high-speed data acquisition systems, industrial control and factory automation systems. Its package pins are shown in Figure 3. The pin function description is as follows: ANLG IN is analog input; it is chip select, low effective; DO~D3, D4~D7 are three-state data outputs; it is the interrupt output terminal, indicating the end of conversion; MODE is the mode selection input; it is the overflow flag; it is the read input terminal; REF- is the reference voltage lower limit; REF+ is the reference voltage upper limit; VCC is the power supply voltage; it is the write input/read status output.

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2.3 Altera-FPGA and ARM processor
The FPGA of this system is implemented by EP2C35 of CycloneⅡ series of Altera FPGA. EP2C35 provides up to 33,216 logic units (LE), 35 18×18-bit multipliers, 483,840-bit internal RAM blocks, dedicated external memory interface circuits, 4 phase-locked loops (PLLs) and high-speed differential I/O functions.
The ARM processor used in this system is Philips' LPC2210, which is a microcontroller based on a 16/32-bit ARM7TDMI-S CPU that supports real-time simulation and embedded tracing. The 144-pin package, extremely low power consumption, two 32-bit timers, eight 10-bit ADCs, PWM outputs and up to nine external interrupts of LPC2210 make it particularly suitable for industrial control, medical systems, access control and electronic cash registers. Through configuration, LPC2210 can provide up to 76 GPIOs. With a wide range of built-in serial communication interfaces, it is also very suitable for communication gateways, protocol converters and various other types of applications.

3 Overall implementation plan of the acquisition system
3.1 FPGA controls A/D chip to collect accelerometer data
The accelerometer uses two analog voltage outputs to reflect the magnitude of the acceleration value. When the acceleration value is 0, the output voltage is 1.50 V, the voltage output sensitivity is 150 mV/g, and the analog input voltage range of the A/D converter is VCC±0.1 V. The analog input voltage lower than VREF-+(1/2)LSB or higher than VREF+-(1/2)LSB is converted to 00000000 or 1111111 respectively. The voltages applied in the system are VCC=VREF+=5 V, VREF-=GND=OV. TLC0820 can work in read-only and read-write modes through the setting of MODE. When MODE is low, the converter is in read-only mode. In this mode, as output, and as the ready output terminal; at the same time. When is low, it is also low, indicating that the device is busy. The converter starts converting at the falling edge of, and the conversion is completed in less than 2.5μs. At this time, it falls. When MODE is high, the converter is in read/write mode and serves as a write output. When MODE is low, the converter starts to measure the input signal and returns to high after about 600 ns. The converter completes the conversion and starts the conversion at the rising edge in the read/write mode. This experiment uses the read/write mode to control the A/D chip to read the value of the accelerometer. The required control signal is output by the FPGA. The related logic control is written in the Verilog hardware description language. Figure 4 is the top-level module diagram of the FPGA connecting the A/D chip and the ARM system in QuartusⅡ.

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The 8-bit digital signal converted by the A/D converter can be read from the built-in logic analyzer of QuartusⅡ. Figure 5 is a screenshot of the read data value viewed through the built-in logic analyzer of QuartusⅡ software. It can be seen from Figure 5 that in the read-write mode, the conversion starts at the rising edge of WR/RDY and is completed at the falling edge of INT. The conversion time can be calculated through the time ruler, which is 24×40=960 ns. After that, the converted data can be read into the data bus through the rising edge of RD, as shown in XDD and YDD in Figure 5. Because the processing speed of the microcontroller is generally lower than the speed of the A/D conversion chip, the data of XDD and YDD are stored in the FIFO in the FPGA, and the FIFO plays the role of data buffering in preparation for the microcontroller to read the data next.

3.2 ARM system receives FPGA data
Figure 6 is a block diagram of the transmission interface between FPGA and ARM. The ARM system mainly controls the start of data acquisition and the display and storage of data after acquisition. During the data acquisition process, the ARM processor system reads the data in the FPGA, which is actually reading the data in the FIFO. The capacity of the FIFO can be set by software. It has two status display signals, ALFUL and EMPTY. ALFUL means that the FIFO is close to full. When ALFUL changes from low level to high level, the ARM microcontroller system can send the RDFIFO signal to read the data output port in the FIFO. When the EMPTY signal in the FIFO changes from low level to high level, it indicates that there is no data to read in the FIFO, and the ARM microcontroller starts waiting for the jump of ALFUL for the next reading.

3.3 Acceleration data display and storage
The data collected by the ARM system can be sent to the host computer through the serial port line for real-time display, and can also be stored in the IDE hard disk by simulating the IDE communication protocol. The LPC2210 communicates with the host computer through the serial port line mainly by using the universal asynchronous receiving/transmitting device UART0 in the ARM chip LPC2210, and using the universal programmable I/O port of the LPC2210, it can simulate the read and write timing of the IDE hard disk and realize the read and write operations of the storage device. In this way, the acceleration data can be displayed and stored.

4 Conclusion
Here we introduce a data acquisition design scheme for a micro-accelerometer of a MEMS device. Combining the currently widely used processing chips ARM and FPGA, a data acquisition scheme with flexible configuration and strong versatility is given. In the experiment, the acceleration signal of the MXR6150G/M accelerometer of the MEMS can be accurately collected. The collected signal can be displayed in real time on the host computer and stored in the IDE interface hard disk, achieving the purpose of data display and storage.