Implementation and Application of FPGA Reconfigurable Configuration Method Designed by ARM

With the rapid development of semiconductor process technology, the integration of field programmable logic devices (FPGAs) has increased rapidly and has reached the level of millions of gates. At the same time, the logic resources in FPGAs are becoming increasingly abundant, making FPGA-based system-on-chip design possible. FPGA-based system-on-chip design has become a research hotspot in electronic system design because of its advantages of short development cycle, low design cost, programmable software and hardware, flexible system design, scalability, expandability, and upgradeability, and has been put into practical application in the fields of communications, industrial control, etc.

At present, FPGA can be classified into FPGA based on LUT (lookup table) technology, SRAM process, nash technology and anti-fuse technology, and the most used FPGA is based on SRAM technology, such as Altem's Cyclone and Stix series, Xilin's Spanan and Virtex series. SRAM-based FPGA has SRAM on the chip to store configuration bit stream. When powered on, the configuration information stored in the dedicated configuration chip is loaded into the FPGA to achieve certain logic functions. When the power is off, the configuration data in the SRAM on the chip is lost and the configuration needs to be reloaded when the power is turned on next time. This structure of storing configuration data in the volatile memory on the chip allows the FPGA to dynamically update the configuration data in its SRAM online, thereby realizing the dynamic change of circuit logic function. System reconfiguration is mainly achieved by using the dynamic reconfiguration feature of SRAM-based FPGA. The following is an analysis of the configuration method and reconfigurable application of Altem's Cyclone II series FPGA.

1 Reconfigurable Configuration Method

According to the role of FPGA in the configuration process, the configuration modes of Cyclone II series FPGA can be divided into three types: FPGA active serial (As) mode, FPGA passive serial (PS) mode and JATG mode. Different configuration modes are selected through the configuration mode selection pin MsEL[1:0]. When MsEL[1:0]=o0, As mode is selected, and when MsEL[1:0]=01, PS mode is selected. For some serial configuration devices, when MsEL[1:0]=l0, it is fast AS mode, and the configuration speed is twice as fast as PS mode. Cyclone II series FPGA supports self-decompression of configuration data, and stores the compressed configuration data in the configuration device or other memory. When configuring, the compressed bit stream data is transmitted to the FPGA. The FPGA can decompress and program the internal SRAM in real time. The compression ratio of configuration data can reach 35%-50%, which can effectively save configuration storage space.

In the AS mode, the FPGA actively outputs control and synchronization signals to the dedicated serial configuration chip. After receiving the configuration command, the configuration chip starts to send the configuration data serially to the FPGA to complete the configuration work. Currently, the commonly used dedicated serial configuration chips are EPCS4 with a capacity of 4 Mb and EPCS16 with a capacity of 16 Mb. The AS configuration mode mainly uses four signals: serial data input DcLK, control signal input AsDI, chip select signal ncs and serial data output DATA.

In PS mode, the configuration process is initiated by other devices in the system. FPGA only outputs response signals during the configuration process. The device that initiates the control configuration process can be a processor, Altem EPC series configuration chip, CPLD and other functional devices. The PS configuration mode will be introduced in detail in the next section. The JTAG debugging interface has been integrated into the chip as a standard interface, mainly used for chip testing. Cycle0ne II series FPGAs all support JTAG mode to configure FPGA. JrI'AG mode has a higher priority than other configuration modes. JrI'AG interface defines four standard signals:

● rI℃K test clock, all signals need to be synchronized with the test clock;

● TDI test data input, test data serial input, data is transmitted on the rising edge of TCK;

● TDO test data output, test data serial output, data is transmitted on the falling edge of TCK;

●TMs test mode selection determines the changes in the TAP controller state machine inside the JTAG circuit.

2 Configuration method and implementation based on ARM

2.1 PS Configuration Principle

As shown in Figure 1, the internal logic of EP2c20 is reconstructed in a passive serial manner using s3c2410x as the main controller. The PS configuration method of FPGA is a commonly used configuration method, which can effectively realize the online configuration of FPGA. Its basic process is: connect the FPGA passive configuration method configuration interface to the IO pin of the ARM processor in the system, and control the high and low levels of the corresponding pins on the processor side through software to send data serially to the FPGA. The reconstruction program runs in the ARM processor as a task of the real-time system. When the internal logic of FPcA needs to be reconfigured, the corresponding task is called. After the configuration is completed, the current task can be deleted. Therefore, the pre-established configuration file library can be stored in ARM's nash, and the configuration program running in the ARM processor can complete the dynamic reconstruction task. The pin functions related to the FPGA and PS configuration methods are shown in Table 1:

The timing diagram of several key signals in the entire configuration process is shown in Figure 2. The configuration process can be divided into three stages: reset, configuration, and initialization:

In the reset phase, the microprocessor first generates a negative pulse with a width greater than 8 s on the ncONFIG signal line, and then starts to detect the state of the nsTATus signal. After the FPGA detects the falling edge of the ncONFIG signal, it will force the nsTATus and ncONF-DONE signals to be pulled low, putting the FPGA in the reset state. When ncONFIG becomes a high level, the FPGA exits the reset state and releases the open-drain nSTATUS pin. The nSTATus pin needs to be pulled high by a 10K pull-up resistor externally. After the nSTATUS pin becomes a high level, the FPGA enters the configuration phase. At this time, the FPGA is ready to receive configuration data.

After the FPGA's nsTATuS pin goes high, there is a delay of about 5 seconds. At the rising edge of DCLK, the FPGA can receive the configuration data serially from the DAL0 pin. The configuration data is sent out from the data line in the order of low bits first and high bits last. When all the data are received, the open-drain CONFIG-DONE pin is released. The CONFIG-DONE pin needs to be pulled high by a 10K pull-up resistor externally. The jump from low to high of the CONFIG-DONE pin indicates the end of the configuration phase and the FPGA enters the initialization phase. If an error occurs during the configuration process, the nrATus pin will output a low level, and the FPGA will automatically reset internally. The processor can determine whether an error has occurred during the configuration process by querying the status of the ns1IATuS pin. If the nsTATuS pin becomes low during the configuration process, it indicates that an error has occurred. If the option of automatically restarting configuration after an error occurs is set in the software, the FPcA will release nsTATuS after a delay. At this time, nsTATuS is pulled high by the external pull-up resistor, and the CPu restarts the configuration after detecting a jump from low to high on nsTA-Tus. If the "automatically restart configuration after an error occurs" option is not set in the software, the CPu needs to first set the nCONFIC pin low and then pull it high to start reconfiguration.

During the initialization phase, the initialization clock can be the FPGA internal clock or the external clock provided by the CLKusR pin. In this example, the FPGA internal clock is used, and the FPGA will provide the clock for initialization. In this way, the initialization phase no longer requires an external clock. After the initialization phase is completed, the INIT-DONE pin becomes high, indicating that the FPGA has successfully entered the user mode and the configuration process is completed. It should be noted that if CONF-DONE or INIT_DONE does not become high at this time, it means that the configuration process is unsuccessful and the CPU needs to reconfigure. [page]

2.2 Configuration Program Design

The following is the complete reconstruction program and flow chart (as shown in Figure 3), which runs as a task of the μC/OS-II real-time operating system of the s3c2410x ARM processor, but in engineering applications, appropriate modifications should be made based on actual conditions.

Based on μC/OS-II configuration program:

U8Fpga～DownLoad(v0id)

{U8 Bootaddr;

U32 CountNum =0:

u8 Fpga is not as good;

U16 i:

Bo0taddT: (u8 )(O](33ooooo0); / Configuration data starting address /

SeI—Datao(O);

seLnCONFIG(0);/_Set ncONFIG to low level/

set_DCLK(O);

hude1ay(10); // Delay 1O ／

if(ReturnSTATUS)

{prin ("err0r: nSTATuSis 1 1");

return O;}

Set— nCONFIG(1);

while(!Read_nsTATUS);

hudelay(5);

p nd("十co gIlre FPGA.-);

while(c0untNum <=O)(24294)／}Serial configuration data／

{FpgaBuer= (Bo0t&ddT+c0un um);

if(!(CountNum%1O24))pdnd(".");

f0r(．_O；i<8；i++)

{Set_Data0(FpgaBus1);

hudelay(1);

seLDCLK(O);

FpgaBusr>>=1;

if(!ReaⅡ_ns1,ATUS)

{ nEf(”＼n, BU C0 gure Error: nsTATus is 0 1, n);

ren】m O；}

Set_DCLK(1);

}

C0untNum++:

}

SeI—Datao(O);

SeI—DCLK(O);

if(!Reau—nsTATuS)

[page]

{p ntf(”, n＼r—Configure Ermr: nsrATus is O!, n, r );

return O; }}

else if (Read_nCONF_Done)

{p ntf(”＼n＼BU-Co gure success! ,n );}

fnr(i=O；i(5O；i++)／ Initialization／

{Set_DcLK(1);

hudeIay(1);

Set_DCLK(O);

hude1.dy(1);},

if(!Read—nCONF—D0ne)

{printf(”, r＼n—configure En r：nCO F—Done is 0 1”);

return 0: }

return l:

{

3 Reconfigurable Configuration Application

Combined with the above reconfigurable configuration analysis, we use the reconfigurable characteristics of FPGA to realize the design of modular robot controller. Modular robots have complex structures, a large number of control motors, and different control strategies for different configurations. For example, the four-degree-of-freedom serial manipulator configuration and the omnidirectional mobile car configuration (as shown in Figure 4) are very different from the control strategy to the number of control motors. This requires the controller to be able to dynamically change the control strategy according to different configurations, that is, the controller is reconfigurable. To this end, in the design of the modular robot reconfigurable control module structure, a dynamically reconfigurable modular robot control system based on ARM and FPGA is proposed, making full use of the high performance, low power consumption, and rich resources of the embedded ARM core microprocessor and the reconfigurable characteristics of the internal logic of FPGA. The main processor selects different control strategies according to the current configuration of the robot and dynamically reconfigures the internal logic of FPGA to adapt to the needs of different configurations and applications. The structural design block diagram is shown in Figure 5.

The ARM module uses s3c2410x to run C/OS-II real-time operating system, which is responsible for running the control software, completing the motion planning of the modular robot, real-time monitoring of the system operation status, realizing the human-computer interaction function and real-time reconstruction of the internal logic of the FPGA. The soft-core processor runs inside the FPGA and is responsible for tasks related to the motion control of the modular robot, such as steering gear control, DC motor control, system IO control, sensor data acquisition, etc.

The ARM-based PS configuration method mentioned above is used for FPGA configuration. The platform makes full use of the reconfigurable characteristics of the internal logic of FPGA and can form a variety of different configurations. Different configurations have different physical structures and control methods to meet different task requirements. The reconstruction method adopts:

(1) Plan the types of system hardware resources according to the specific configuration, such as the number of DC motors, the number of servos, the number of system I/Os, and the number of various sensors required by the configuration.

(2) Modify the internal logic of FPcA according to the type of hardware resources to achieve "reconstruction" at the hardware level.

(3) Develop software based on changes in FPGA logic to achieve "reconstruction" at the software level.

(4) Download the FPGA configuration file to the ARM memory. After the system is powered on, ARM reads the configuration file in the corresponding storage area according to the requirements.

The FPGA is configured using the configuration file to achieve dynamic reconstruction of the control system.

The experimental results show that the designed control platform can meet the performance requirements of reconfigurable configuration by utilizing the real-time processing function of ARM and dynamically reconfiguring the internal logic of FPGA.

4 Conclusion

This paper presents a PS loading configuration scheme for FPGA based on ARM. This method has a simple circuit structure and is easy to implement. It makes full use of the characteristics of ARM processor, which is powerful, fast and widely used. Multiple configuration files with different functions can be included in the system in advance. The corresponding configuration can be performed according to the needs of the site to realize the online update of FPGA function. It not only saves development costs, but also meets some special system design requirements. It also fully demonstrates the design concept of FPGA on-site upgrade and flexible application. The proposed scheme has considerable reference significance for the design of embedded digital systems.