Design of ISP1362OTG based on AVR microcontroller

0 Introduction

With the popularity of consumer products such as PDAs, mobile phones, digital cameras, printers, etc., the high-speed data transmission technology used for these devices and computers, or between devices, has attracted more and more attention. In the past, the data transmission structure with computers as the core was not conducive to the application of USB, bus in the embedded industry, and was not suitable for field operations. The introduction of OTG technology can realize data transmission between devices without PCs, which expands the application scope of USB technology. The design scheme adopted in this paper is based on Philips' ISP1362 OTG control chip. Referring to the latest USB OTG technical specifications, a master/slave system that complies with the USB protocol is designed.

1 Internal structure of ISP1362 chip

Philips' ISP1362 is an interface chip that complies with the USB 2.0 bus protocol. It has three USB controllers inside: a host controller, a device controller, and an OTG controller. The host controller has highly optimized USB host functions; the device controller has up to 14 programmable endpoints, which can be configured as double-buffered endpoints to further improve throughput; and the OTG controller mainly provides all OTG controls including monitoring and conversion functions. The internal structure of ISP1362 is shown in Figure 1.

2 USB OTG master/slave system design

The design of USB OTG master/slave system includes two modules: hardware design and software design. The hardware circuit mainly includes the design of USB interface circuit board; the software design includes device initialization, system function design, device driver design, etc. The following introduces the design methods of system software and hardware system respectively.

2.1 System hardware circuit design

The hardware circuit of USB OTG master/slave design is shown in Figure 2. In the figure, the PD port and IPA port of ATmega 32 are used to control the timing of ISP1362, and the PB port and PC port are used to exchange data with D[0. 15] of ISP1362. The ISP1362 chip has two USB interfaces, Port1 and IPort2. Port1 is a comprehensive interface that can be configured as downstream, upstream or OTG; Port2 is a fixed downstream and is mainly connected to general USB devices. When ISP1362 acts as a host, the register inside the host can determine whether Port1 or Port2 is connected to a device by detecting the value of its corresponding status register, and then perform corresponding processing.

The master/slave function of Port1 of ISP1362 is determined by the combination of the high and low levels of the two pins ID and OTGMODE. When the OTGMODE pin is low, regardless of the ID level, the chip's Port1 can only be used for OTG; if OTGMODE is high and ID is low, the chip's Port1 is used as a host; when OTGMODE is high and ID is also high, the chip's Port1 is used as a peripheral. In the circuit, the high and low changes of the levels of the two pins ID and OTGMODE are realized through 15kΩ pull-up resistors and pull-down resistors.

2.2 System software design

The host system of this design is a collection of software and hardware. The implementation of its functions does not depend on any operating system. Instead, it schedules various tasks through interrupts to meet the requirements of USB communication. Therefore, the system runs in accordance with protocol specifications and specific timing.

This system is an application of ISP1362 working in master/slave mode. After the interface chip is configured according to the system hardware circuit, it can be programmed to perform USB data transmission. The system workflow is as follows: first, the system is initialized, the PTD transmission descriptor is constructed, and then the bus enumeration process is performed to assign addresses to peripherals, obtain basic information about the peripherals, and determine whether the peripherals are host devices or slave devices. Then, the corresponding master/slave driver is driven to run, data is transmitted and received, and whether it is suspended is determined according to the activity of the bus. The system flow chart is shown in Figure 3:

To realize software programming control of ISP1362 chip, we need to control the CS, RD, WR, A0 and A1 pins of the chip. In this article, CS stands for chip select, which is valid at low level; RD stands for read signal, which is valid at low level; WR stands for write signal, which is valid at low level; the different levels of A0 pin indicate whether the transmitted signal represents command signal or data signal; the different levels of A1 pin indicate whether the control is peripheral or host. Through the combination of the above pin signals, different functions of read and write control of ISP1362 can be realized. In addition, the following pins are also of great significance for controlling ISP1362: DREQ1 pin represents DMA request output, when it is high level valid, it notifies IDMA controller that host is requesting data transfer; DREQ2 pin is high level valid, it notifies DMA controller that peripheral is requesting data transfer; DACK1 pin represents DMA confirmation input, when low level valid, it indicates that DMA transfer request from host has been confirmed by DMA controller; DACK2 pin is low level valid, it indicates that DMA transfer request from peripheral has been confirmed by DMA controller; INT1 and INT2 pins are connected to IRQ pin of external microprocessor, so that ISP1362 can execute interrupt service program according to request. The specific workflow of software design is as follows:

(1) System hardware initialization, including the initialization of ATmega32 and ISP1362. AVR microprocessor is an 8-bit embedded RISC processor of Atmel. It has the advantages of low power consumption, high speed, high output, open development tools, and high cost performance. Its program memory and data memory are Harvard structures that can be accessed independently, so the code execution efficiency is very high. The internal modules of the ATmega series microcontrollers are also very rich, and there are many available resources. The initialization of ATmega32 in this article is to set its I/O ports, timers, clocks, watchdogs, etc. accordingly to make it start working. The initialization of ISP1362 means that when ISP1362 is powered on, the host controller driver (HCD) must go through a series of hardware initialization steps to configure the host controller so that it can enter an operational state. First, check whether the host controller exists. This step is implemented by MCU (single-chip microcomputer). This article writes a value into the HcScratch register through MCL response, and then reads from the register, and compares the read value with the written value. If they are equal, it means that the host controller exists; otherwise, an error occurs and no host controller exists.

(2) Construct PTD descriptor. PTD (Phi l ips Transfer Descriptor) provides a transmission channel for the communication between the ISP1362 host controller and the peripheral devices. To communicate between the host and the peripheral devices, you need to construct a PTD first. PTD has three types of transmission: control and bulk transfer (non-periodic transfer) PTD, interrupt transfer PTD and synchronous transfer PTD.

(3) The host assigns an address to the device and obtains the device descriptor and device function information. The host obtains the function information of the device and endpoint by continuously sending device requests to the peripheral. The process of obtaining the USB device descriptor is divided into three steps: a. The host obtains the device descriptor through the default endpoint of the device and assigns a unique address to the device; b. The host reads the configuration descriptor information, interface descriptor information and endpoint descriptor information; c. Calls the corresponding transaction handler according to the relevant information of the device.

(4) After the device is enumerated successfully, the host can communicate with the peripheral device via USB according to the programmed process, waiting for and querying the sending and receiving of data.

(5) After the data is sent or received, the QueryBus function queries the bus activity to determine whether the device needs to be suspended.

2.3 Device Drivers

To realize the host to the slave read and write, the USB host must have a corresponding driver to encapsulate, interpret and execute various read and write instructions. There are many ways to develop drivers. This article uses a USB transfer API function - USBXfer directly encapsulated on the upper layer of the USB host interface driver to implement various USB transfers.

3 Conclusion

The USB 0TG master-slave system designed in this paper has stable performance and high data transmission efficiency. Tests show that this design can correctly realize the data exchange between USB 0TG master and slave, and the performance can meet the data transmission requirements between devices, while also being able to control costs well, and has certain practical value.