[HC32F460 Development Board Review] 07 Clock Configuration of ADC Acquisition Process

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[HC32F460 Development Board Review] 07 Clock Configuration of ADC Acquisition Process [Copy link]

 

I have learned STM32F103VCT6 before, but I just modified the program and didn’t learn it in depth. I didn’t understand specifically how the internal clock is divided and multiplied.

Now it is a good opportunity to learn more about the internal clock of this microcontroller through Huada's HC32F460 development board.

By the way, record your own learning records.

The process used here is the adc_01_sa_base process of the ADC part of the development board.

Before starting, I took a quick look at the bus architecture of the chip, in the user manual 2 Bus Architecture (BUS) section;

I studied ST chips before, but I didn't look at them because they seemed too complicated. Now the price of ST chips has skyrocketed, and everyone is looking for domestic chips.

Under this situation, I became interested in microcontrollers again, and now I am re-learning the things that I found complicated before.

The bus architecture actually realizes the interconnection between the host bus and the slave bus. From this we can see which specific peripheral resources the host bus can access.

This picture shows the interconnection between the host bus and the cluster bus in the form of a matrix. Now it seems that it is not as complicated as previously imagined.

It may be that I was not that interested in it before, and I was more involved in hardware. My teammates in school were specialized in writing code, and I learned less, so this part is relatively weak.

The adc_01_sa_base process only contains the configuration of ADC related clocks. Here we record it to have a specific understanding of the ADC clock configuration process.

The configuration function of the ADC clock ( AdcClockConfig() ) is in the AdcConfig() function of this process .

The following is the specific code of the function AdcClockConfig() :

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The code first makes a judgment on ADC_CLK. From the very beginning of the process, you can see its macro definition #define ADC_CLK (ADC_CLK_UPLLR)

So the main code of this function is the content between the second #elif....#endif .

1. UPLL clock source selection

The following code mainly selects XTAL as the clock source of UPLL. The configuration of this part mainly assigns the corresponding value to the variable stcXtalCfg

The stcXtalCfg variable is a structure, and the corresponding structure members can be viewed in the structure definition part.

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2. UPLL related configuration

The following is the configuration of UPLL, which mainly configures the clock source specifications. The user manual 4.3 Clock Source Specifications has a corresponding introduction:

UPLL Clock (UPLL)

Input clock: external high-speed oscillator or internal high-speed oscillator UPLL input clock division: 1~24 arbitrary division optional VCO input frequency = input clock/UPLL input clock division, frequency range 1MHz~24 MHz UPLL multiplication factor: 20~480 times VCO oscillation frequency: 240MHz~480M Hz UPLLP output division ratio: 2~16 arbitrary division UPLLQ output division ratio: 2~16 arbitrary division UPLLQ output frequency division ratio: 2~16 arbitrary frequency division UPLLP output frequency = (input clock/UPLL input clock frequency division) *UPLL frequency multiplication factor /UPLLP output frequency division ratio UPLLQ output frequency = (input clock/UPLL input clock frequency division) *UPLL frequency multiplication factor/UPLLQ output frequency division ratio UPLLR output frequency = (input clock/UPLL input clock frequency division) *UPLL frequency multiplication factor/UPLLR output frequency division ratio

The above table is a section of information related to the UPLL clock source.

a. Input clock: external high-speed oscillator or internal high-speed oscillator
From this, we can know that the input clock is either an external high-speed oscillator or an internal high-speed oscillator . The clock source selection has been configured in 1. UPLL clock source selection and the external high-speed oscillator is selected as the clock source;

b. UPLL input clock frequency division: 1~24 arbitrary frequency division optional VCO input frequency = input clock /UPLL input clock frequency division, frequency range 1MHz~24MHz

From stcUpllCfg.pllmDiv = 2u; we know that the UPLL input clock is divided by 2, so the corresponding VCO input frequency is 4MHz ( the input clock is XTAL 8MHz, divided by 2);

c. UPLL frequency multiplication factor: 20~480 times

From stcUpllCfg.plln = 60u; we know that the UPLL multiplication factor is 60.

d. VCO oscillation frequency: 240MHz~480MHz UPLLR output frequency = (input clock/UPLL input clock frequency division) *UPLL frequency multiplication factor/UPLLR output frequency division ratio

So the VCO oscillation frequency is 4MHz*60=240MHz

e. UPLLP output frequency division ratio: 2~16 arbitrary frequency division
UPLLQ output frequency division ratio: 2~16 arbitrary frequency division

UPLLR output division ratio: 2~16 arbitrary division is determined
by stcUpllCfg.PllpDiv = 16u;
stcUpllCfg.PllqDiv = 16u;
stcUpllCfg.PllrDiv = 16u; we know that UPLLP, Q, R are all divided by 16

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The clock configuration for ADC acquisition ends here.

Before I knew it, the review activity of the Huada side review board was about to end, and I still hadn't watched the PGA that I was most interested in. I worked during the day, and reviewed and prepared for the exam on weekends and at night. I was squeezing time to study intermittently. I have to say that the learning atmosphere of the forum is quite good. Without this learning atmosphere, I probably wouldn't be able to learn between working and reviewing. I come to the forum when I have time and learn something, hahaha.