ARM learning notes 1 (ARM overview and its basic programming model)

Overview of arm and its basic programming model
Versions and naming methods of

arm architecture Features of the 6 versions of

arm architecture Variants of the arm system

1 thumb instruction set (t variant)
2 long multiplication instructions (M variant)
3 enhanced dsp instructions (E variant)
4 java accelerator jazelle (J variant)
5 arm media function extension (SIMD variant)

Naming format of arm/thumb system version
1 string ARMv
2 ARM instruction version number 1-6
3 character indicating variant version 4 After that, the M variant becomes a standard function and does not need to be listed
4 Use x to exclude a certain write function

arm processor series
arm7
arm9
arm9e
arm920T ARM922T ARM9440T
arm10e
securCore
intel's Xscale
intle's StrongARM

ARM processor mode
7 operating modes
User mode (User, usr) Normal program execution mode
Fast interrupt mode (FIQ, fiq) Used for high-speed data transmission and channel processing
External processing interrupt mode (IRQ, irq) Used for normal interrupt processing
Privileged mode (Supervisor, sve) A protection mode for operating systems
Data access abort mode (Abort, abt) Used for virtual storage and storage protection
Undefine mode (Undefine, und) Used to support hardware coprocessors through software guidelines
System mode (System, sys) Used to run privileged operating system tasks

Registers in various processing modes

The working mode can be changed by software, or by external interrupts or exception processing

Modes other than user mode are called non-user modes, privileged modes (privileged modes)
Modes other than user mode and system mode are called exception modes (exception modes)

ARM register introduction
ARM has a total of 37 registers and
31 general registers
Divided into the following three categories:
unbacked registers (the unbanked registers) r0-r7
refer to the same physical register
Can be used in any application that uses general registers
Backup registers (the banked registers) r8-r14
Each register of r8-r12 corresponds to two different physical registers.
Each register of r13-r14 corresponds to 6 different physical registers, one of which is shared by user mode and system mode, and the other 5 correspond to the other 5 processing modes. Use R13_ to distinguish physical registers.
The mode can be the following modes: usr svc abt und irq and fiq
r13 is often used as stack pointer sp
r14 is also called link register lr. The functions of the two special columns
Store the return address of the current program
Sample code:
MOV PC, LF
BX LR
Use the following instruction at the subroutine entry to save PC to the stack
STMFD SP!, {, IR}
Subroutine returns
LDMFD SP!, {, PC}
When an exception interrupt occurs, set it to the address to be returned by the exception mode

Program counter PC r15
pc points to the address of the next two instructions of the current instruction. The 0th and 1st bits are always 0.
Try to avoid using STR/STM instructions to save R15

6 status registers
CPSR (current status register), can be accessed in any processing mode
Each processing mode has a physical status register (except user mode and exception interrupt mode), SPSR (backup program status register), which stores the contents of the current status register when a specific exception interrupt occurs.

The format of cpsr is as follows:
31 30 29 28 27 26 7 6 5 4 3 2 1 0
N Z C V Q DNM (RAZ) I F T M4 M3 M2 M1 M0

conditional flag
N (negative) z (zero) c (carry) v (overflow)
arm instructions are selectively executed according to the conditional flag in cpsr, and

instructions that affect the conditional flag
Comparison instructions cmp cmn teq tst
When the target register of arithmetic and logical instructions is not r15,
the msr instruction can write a new value to the cpsr/spsr.
The variant of the ldm instruction can copy the value of spsr
to Some variants of arithmetic and logical instructions with "bit set"

Q flag Bit
used to indicate whether an enhanced dsp instruction overflowed
the cpsr[27]
Bit [27] of spsr
For processors before arm v5 or non-e series, the q flag is not defined.

Control bits in cpsr
The lower 8 bits of cpsr IFTM [4:0]

Interrupt disable bit
When I=1, IRQ interrupt is disabled
When F=1, FIQ interrupt is disabled

The T control bit is used to control the execution status of the instruction (indicates whether the instruction is an arm instruction or a thumb instruction)
arm v4 t series
T=0 indicates arm instruction
T=1 indicates thumb instruction
arm v5 non-t series
t=0 indicates arm instruction
t=1 indicates that the next instruction to be executed will generate an undefined instruction interrupt

M control bit controls the processor mode
M[4:0] Processor mode Registers that can be accessed
0b10000 user pc r14-r0 cpsr
0b10001 fiq pc r14_fiq-r8_fiq r7-r0 cpsr spsr_fiq
0b10010 irq pc r14_irq-r13_irq r12-r0 cpsr spsr_irq
0b10011 supervisor pc r14_svc-r13_svc r12-r0 cpsr spsr_svc
0b10111 abort pc r14_abt-r13_abt r12-r0 cpsr spsr_abt
0b11011 undefined pc r14_und-r8_und r12-r0 cpsr spsr_und
0b11111 system pc r14-r0 cpsr

Exception interrupt of arm system The
arm system has three ways to control the execution flow of the program
1 During the normal program execution, each time an arm instruction is executed, the value of the program counter register (pc) is increased by 4 bytes; executing a thumb instruction increases the value by two bytes
2 Through the jump instruction, jump to a specific address label for execution, or execute a specific subroutine,
b instruction performs a jump operation
bl instruction performs a jump and saves the return address of the subroutine
bx instruction performs a jump and switches the program state to thumb state according to the lowest bit of the target address
blx is the superposition of the above two instructions