LPC824-SPI interface (continued one)

The SPI interface involves a total of 11 registers. Let’s analyze them in detail below.

Let’s first look at the SPI configuration register CFG. The following table shows its entire bit structure. Its addresses are 0x40058000 (SPI0) and 0x4005C000 (SPI1).

(1) Bit 0 (ENABLE) is the SPI enable bit. When the value is 0, the SPI interface is disabled. When the value is 1, the SPI interface is enabled. The default is disabled.
(2) The first bit is a reserved bit, and only 0 can be written when writing.
(3) Bit 2 (MASTER) is the master mode selection bit. When the value is 0, it is the slave mode. At this time, the SCK, MOSI and SSEL signals are input, and MISO is the output. When the value is 1, it is the master mode. At this time, SCK , MOSI and SSEL signals are output, MISO is input, and the default is slave mode.
(4) Bit 3 (LSBF) is the LSB priority mode enable bit. When the value is 0, it is the standard mode, and the data is sent and received in the standard MSB priority order. When the value is 1, it is the reverse mode, and the data is sent in the reverse order. and receive (LSB first), defaulting to standard mode.
(5) Bit 4 (CPHA) is the clock phase selection bit. When the value is 0, it is the change mode. SPI captures the serial data during the first clock transition of the transmission (at this time, the clock changes to the opposite direction of the idle state). The data changes on the next edge. When the value is 1, it is the capture mode. SPI changes the serial data when the first clock transition of the transmission (at this time the clock changes to the opposite direction of the idle state), and captures the data on the next edge. The default is change. model.
(6) Bit 5 (CPOL) is the clock polarity selection bit. When the value is 0, it is low level, that is, the clock idle state (between two transmissions) is low level. When the value is 1, it is high level. That is, the clock idle state (between two transmissions) is high level and the default is low level.
(7) Bit 6 is a reserved bit, and only 0 can be written when writing.
(8) Bit 7 (LOOP) is the loopback mode enable bit. The loopback mode is only applicable to the host mode. It connects the sending and receiving data and supports simple software testing. When the value is 0, it is disabled. When the value is 1, it is disabled. Enabled, disabled by default.
(9) Bit 8 (SPOL0) is the SSEL0 polarity selection bit. When the value is 0, it selects active low level. When the value is 1, it selects active high level. The default is active low level.
(10) Bit 9 (SPOL1) is the SSEL1 polarity selection bit. When the value is 0, it selects active low level. When the value is 1, it selects active high level. The default is active low level.
(11) Bit 10 (SPOL2) is the SSEL2 polarity selection bit. When the value is 0, the low level is valid. When the value is 1, the high level is valid. The default is low level.
(12) Bit 11 (SPOL3) is the SSEL3 polarity selection bit. When the value is 0, it selects active low level. When the value is 1, it selects active high level. The default is active low level.
(13) Bits 12 to 31 are reserved bits, and only 0 can be written when writing.

Next, look at the SPI delay register DLY. The following table shows its entire bit structure. Its addresses are 0x40058004 (SPI0), 0x4005C004 (SPI1).

(1) Bits 0 to 3 (PRE_DELAY) are used to control the time between SSEL validity and the start of data transmission. There is always 1 SPI clock between SSEL validity and the first clock edge, which is not considered pre-delayed. Part, when the value is 0, it means that no additional delay time is inserted. The value from 0x1 to 0xF means that the delay time of 1 to 15 SPI clocks is inserted respectively. The default is that no additional delay time is inserted.
(2) Bits 4 to 7 (POST_DELAY) are used to control the time between the end of data transmission and SSEL invalidation. A value of 0 indicates that no additional delay time is inserted. Values ​​from 0x1 to 0xF indicate that 1 to 15 SPIs are inserted respectively. The delay time of the clock, the default is that no additional delay time is inserted.
(3) Bits 8 to 11 (FRAME_DELAY) are when the EOF flag is set, it controls the shortest time between the current frame and the next frame (SSEL is invalid if EOT is set). When the value is 0, it means that no additional frame is inserted. Delay time, the value from 0x1 to 0xF respectively indicates the delay time of inserting 1 to 15 SPI clocks. The default is that no additional delay time is inserted.
(4) Bits 12 to 15 (TRANSFER_DELAY) are used to control the minimum time that SSEL is inactive between two transmissions. When the value is 0x0, it means that the minimum time that SSEL is inactive is 1 SPI clock time (zero delta time) , when the value is 0x1, it means that the shortest time for SSEL to be invalid is 2 SPI clock times, and so on. When the value is 0xF, it means that the shortest time for SSEL to be invalid is 16 SPI clock times, and the default is zero increment time.
(5) Bits 16 to 31 are reserved bits, and only 0 can be written when writing. 

Next is the SPI status register STAT. The following table shows its entire bit structure. Its addresses are 0x40058008 (SPI0), 0x4005C008 (SPI1). 

(1) Bit 0 (RXRDY) is the SPI receiver ready flag bit. When the value is 1, it means that data can be read from the receiver buffer. This bit is automatically cleared after reading the RXDAT register.
(2) Bit 1 (TXRDY) is the SPI transmitter ready flag. When the value is 1, it means that the data can be written to the send buffer, possibly before continuing to transmit the data. This bit is automatically cleared when data is written to TXDAT or TXDATCTL. Until the data is moved into the transmit shift register, the default value of this bit is 1.
(3) Bit 2 (RXOV) is the receiver overflow interrupt flag bit. This flag is only applicable to slave mode (Master=0). When a received character is detected but the receiver buffer is being used, this flag If this bit is set, the receiver buffer contents are retained and the input data is discarded. If this bit is set, the data received by SPI should be considered undefined.
(4) Bit 3 (TXUR) is the transmitter underflow interrupt flag bit. This flag is only applicable to slave mode (Master=0). In this case, if the transmitter is idle, the transmitter must input New data is sent when the clock starts. If the data is not available in the transmitter holding register at this time, there is no data available for transmission. This flag is set. If this bit is set, the data sent by SPI should be considered undefined.
(5) Bit 4 (SSA) is the slave selection valid flag. Regardless of the host or slave mode, as long as any slave selects to transition from invalid to valid state, this flag will be set, thus determining the SPI transmit/receive function. This flag must be cleared by software when it becomes busy and allows the device to wake up from low-power mode when a slave mode access is initiated.
(6) Bit 5 (SSD) is the slave selection invalid flag. Regardless of the host or slave mode, as long as any slave selection in the valid state transitions to the invalid state, this flag will be set, so that SPI transmission/reception can be determined When the function becomes idle, this flag must be cleared by software.
(7) Bit 6 (STALLED) is the termination status flag, indicating whether the SPI is in a stop condition.
(8) Bit 7 (ENDTRANSFER) is the transmission end control bit. When the transmitter completes any operation in execution, the software can set this bit to force the end of the current transmission, as if the EOT flag had been set before the last transmission. bit, this feature can provide support for the situation where it does not know when the transmit data was written and is used to end the transmission. As the transmission is about to end, when the transmitter becomes idle, this bit is cleared to zero. This way to force the end of the transfer can insert any specified FRAME_DELAY and TRANSFER_DELAY.
(9) Bit 8 (MSTIDLE) is the host idle status flag bit. As long as the SPI host function is completely idle, this bit is set to 1, which means that the transmit holding register is empty and the transmitter is not performing a data transmission task. This bit The default value is 1.
(10) Bits 9 to 31 are reserved bits, and only 0 can be written when writing.

Next, look at the SPI interrupt enable read and set register INTENSET. The following table shows its entire bit structure. Its addresses are 0x4005800C (SPI0) and 0x4005C00C (SPI1). 

(1) Bit 0 (RXRDYEN) is used to determine whether an interrupt occurs when the receiver data is available. A value of 0 indicates that no interrupt is generated when the receiver data is available. A value of 1 indicates that the receiver data is in the RXDAT register. Generates an interrupt when available. The default is not to generate an interrupt.
(2) Bit 1 (TXRDYEN) is used to determine whether an interrupt occurs when the transmitter holding register is available. A value of 0 indicates that no interrupt is generated when the transmitter holding register is available. A value of 1 indicates that data can be written to TXDAT. When an interrupt is generated, the default is not to generate an interrupt.
(3) Bit 2 (RXOVEN) is used to determine whether an interrupt occurs when a receiver overflow occurs. In slave mode, when the receiver needs to move newly received data to the RXDAT register, which is in use This happens when, in host mode, the interface prevents receiver overflow by not allowing the latest transmission that might cause the receiver to overflow. A value of 0 means that no interrupt will be generated when a receiver overflow occurs. A value of 1 Indicates that if a receiver overflow occurs, an interrupt will be generated. The default is not to generate an interrupt.
(4) Bit 3 (TXUREN) is used to determine whether an interrupt occurs when a transmitter underflow occurs. In slave mode, this happens when data needs to be sent but no data is available. A value of 0 means that no interrupt will be generated when the transmitter underflows. A value of 1 means that if a transmitter underflow occurs, An interrupt is generated, and the default is not to generate an interrupt.
(5) Bit 4 (SSAEN) is used to determine whether an interrupt is generated when the slave selection is valid. A value of 0 indicates that any slave selection from invalid to valid will not generate an interrupt. A value of 1 indicates that any slave selection will not generate an interrupt. The slave selection will generate an interrupt when it changes from invalid to valid. The default is not to generate an interrupt.
(6) Bit 5 (SSDEN) is used to determine whether an interrupt is generated when the slave selection is invalid. A value of 0 means that no interrupt will be generated when all valid slave selections become invalid. A value of 1 Indicates that when all valid slave selections become invalid, an interrupt will be generated. The default is not to generate an interrupt.
(7) Bits 6 to 31 are reserved bits, and only 0 can be written when writing.