The I2C bus is a simple, bidirectional two-wire synchronous serial bus.
The I2C communication protocol is widely used for communication between multiple integrated circuits (ICs) in the system due to its few pins, simple hardware implementation, strong scalability, and the fact that it does not require external transceiver devices for communication protocols such as USART and CAN. .
I2C uses two signal lines to complete information exchange, SCL is the clock signal line, and SDA is the data input/output line.
I2C can support multiple slaves (Slaver) and multiple master modes (Master). Most I2C devices support 100kHz and 400kHz modes, and some special applications can also support 3.4MHz through design.
The simple application of I2C mainly includes two aspects: I2C hardware connection and I2C communication protocol . This article briefly explains the common communication methods.
I2C hardware connection
As shown in the figure below, in an I2C communication bus, multiple I2C communication devices can be connected, supporting multiple communication masters and multiple communication slaves.
SDA, SCL pins and pull-up resistors
The SDA and SCL pins of the device use OD gate outputs, and wired AND operations are performed between different devices, that is, "AND logic".
SDA and SCL require external pull-up resistors. Depending on the number of I2C devices on the bus and the communication speed of the system, different pull-up resistors should be selected in the design. The number of I2C devices determines the size of the bus capacitance on the bus. The bus capacitance and pull-up resistor limit the communication rate of the system.
Normally, the pull-up resistor for 3.3V systems is 3.3kΩ, and the pull-up resistor for 5V systems is 4.7kΩ.
When the I2C device is idle, it will output a high-impedance state. When all devices are idle and all output a high-impedance state, the pull-up resistor will pull the bus to a high level.
Multi-master and multi-slave applications
Each slave device connected to the bus has an independent address, and the host can use this address to access different devices.
When multiple hosts use the bus at the same time, in order to prevent data conflicts, arbitration can be used to determine which host device occupies the bus.
I2C communication protocol
The following figure takes a master (Master) writing one byte of data to a slave (Slaver) as an example to illustrate the basic protocol of I2C communication.
Start signal (S) : When SCL is high, SDA switches from high to low.
Stop signal (P) : When SCL is high level, SDA switches from low level to high level.
Frame address: A unique 7-bit or 10-bit address for each slave device, used for address identification between master and slave devices. The I2C protocol stipulates that the device address can be 7 or 10 bits. In practice, 7-bit addresses are widely used.
Read/write bit: one bit, if the host is sending data to the slave, it is low level, and when requesting data, it is high level.
ACK/NACK: I2C data and address transmission all have responses. The response includes two signals: "ACK" and "NACK". ACK is low level and NACK is high level.
Data is valid: During data transmission, when SCL is high level, the data of SDA is valid, that is, when SDA is high level, it means data "1", when it is low level, it means data "0"; when SCL is low level, The data of SDA is invalid. Generally, at this time, the level of SDA is switched.
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