12.STC15W408AS MCU Comparator

1. Internal structure of comparator

The STC15W408AS microcontroller has a built-in comparator function. The internal layout of the comparator is shown in the following figure:

The level of the comparator positive input terminal CMP+ can be compared with the level of the comparator negative input terminal CMP-, and can also be compared with the internal BandGap reference voltage (near 1.27V).

2. STC15W series special function registers related to comparators

2.1 Comparator Control Register 1: CMPCR1

CMPCR1: Comparator Control Register 1

CMPEN: Comparator module enable bit

        CMPEN=1, enable the comparator module;

        CMPEN=0, disables the comparator module and turns off the power supply of the comparator.

In the case where CMPEN is 1:

When the comparison result of the comparator changes from LOW to HIGH, if PIE is set to 1, then one of the built-in

A register called CMPIF_p will be set to 1;

When the comparison result of the comparator changes from HIGH to LOW, if NIE is set to 1, then one of the built-in

A register called CMPIF_n will be set to 1;

When the CPU reads the value of CMPIF, it will read (CMPIF_p || CMPIF_n);

When the CPU writes 0 to CMPIF, both CMPIF_p and CMPIF_n will be cleared to 0.

The condition for interrupt generation is [ (EA==1) && (((PIE==1)&&(CMPIF_p==1)) || ((NIE==1)&&(CM

PIF_n==1))) ]After the CPU receives an interrupt, it does not automatically clear the CMPIF flag. The user must use software to write "0" to clear it.

PIE: Comparator rising edge interrupt enable bit (Pos-edge Interrupt Enabling)

        PIE = 1, enable the comparator to change from LOW to HIGH event to set CMPIF_p/generate an interrupt;

        PIE = 0, disables the comparator LOW to HIGH event to set CMPIF_p/generate an interrupt.

NIE: Comparator falling edge interrupt enable bit (Neg-edge Interrupt Enabling)

        NIE = 1, enable the event of the comparator changing from HIGH to LOW to set CMPIF_n/generate an interrupt;

        NIE = 0, disables the comparator HIGH to LOW event to set CMPIF_n/generate an interrupt.

PIS: Comparator positive selection bit

        PIS = 1, select ADCIN selected by ADCIS[2:0] as the positive input source of the comparator

        PIS = 0, select external P5.5 as the positive input source of the comparator

NIS: Comparator negative selection bit

        NIS = 1, select external pin P5.4 as the negative input source of the comparator

        NIS = 0, select the internal BandGap voltage BGV as the negative input source of the comparator

CMPOE: comparison result output control bit

        CMPOE = 1, enables the comparison result of the comparator to be output to P1.2;

        CMPOE = 0, disable the comparator comparison result output

CMPRES: Comparator Result flag

        CMPRES = 1, the level of CMP+ is higher than the level of CMP- (or the level of the internal BandGap reference voltage);

        CMPRES = 0, the level of CMP+ is lower than the level of CMP- (or the level of the internal BandGap reference voltage)

This bit is a "read-only" bit; software writing to it has no meaning. The result of the software reading

It is the "result after ENLCCTL control", not the direct output result of the Analog comparator.

2.2 Comparator Control Register 2: CMPCR2

Comparator Control Register 2

INVCMPO: Inverse Comparator Output

        INVCMPO = 1, the comparator is inverted and then output to P1.2;

        INVCMPO = 0, comparator output is normal.

The output of the comparator uses the "result after ENLCCTL control" rather than the direct output result of the Analog comparator.

DISFLT: Remove the 0.1uS Filter from the comparator output

        DISFLT = 1, turn off the comparator output 0.1uS Filter (can slightly increase the comparator speed);

        DISFLT = 0, the comparator output has a 0.1uS filter.

LCDTY[5:0]: Comparator output level-change control filter length (Duty) selection

bbbbbb:=

When the comparator changes from LOW to HIGH, it must detect that the subsequent HIGH lasts for at least bbbbbb clocks.

The analog comparator output is determined to be changed from LOW to HIGH within bbbbbb clocks.

The output returns to LOW, and the chip circuit thinks nothing has happened, and regards the comparator output as always being LOW.

When the comparator changes from HIGH to LOW, it must detect that the subsequent LOW continues for at least bbbbbb clocks.

The analog comparator output is determined to be changed from HIGH to LOW within bbbbbb clocks.

The output returns to HIGH, and the chip circuit thinks nothing has happened, as if the comparator output has always been HIGH.

If it is set to 000000, it means there is no Level-Change Control.

3. Comparator Test Procedure

#include "stc15.h"

void CmpInit();

void main()

{

CmpInit();

EA = 1; // CPU opens interrupt

while (1);

}

// Initialize the comparator module

void CmpInit()

{

// P5.5 is the positive pole of the comparator

// P5.4 is the negative pole of the comparator

// P1.2 is the comparator result output port

CMPCR1 = 0; // Initialize the comparator

CMPCR1 |= 0x80; // Enable the comparator module

CMPCR1 |= 0x02; // Enable the comparison result of the comparator to be output to P1.2

CMPCR1 |= 0x20; // Enable comparator rising edge interrupt

}

//Comparator interrupt service function

void cmp_isr() interrupt 21 //Comparator interrupt vector entry

{

     CMPCR1 &= ~0x40; // Clear completion flag

     P12 = CMPCR1 & 0x01; // Output the comparator result CMPRES to the test port for display

}