【s3c2440】Lesson 5: Timer Interrupt

Introduction to s3c2440 timer

OVERVIEW

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         ~~~~~~~~        The S3C2440A has five 16-bit timers. Timer 0, 1, 2, and 3 have Pulse Width Modulation (PWM) function. Timer 4 has an internal timer only with no output pins. The timer 0 has a dead-zone generator, which is used with a large current device.

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         ~~~~~~~~        The timer 0 and 1 share an 8-bit prescaler, while the timer 2, 3 and 4 share other 8-bit prescaler. Each timer has a clock divider, which generates 5 different divided signals (1/2, 1/4, 1/8, 1/16, and TCLK). Each timer block receives its own clock signals from the clock divider, which receives the clock from the corresponding 8-bit prescaler. The 8-bit prescaler is programmable and divides the PCLK according to the loading value, which is stored in TCFG0and TCFG1 registers.

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         ~~~~~~~~        The timer count buffer register (TCNTBn) has an initial value which is loaded into the down-counter when the timer is enabled. The timer compare buffer register (TCMPBn) has an initial value which is loaded into the compare register to be compared with the down-counter value. This double buffering feature of TCNTBn and TCMPBn makes the timer generate a stable output when the frequency and duty ratio are changed.

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         ~~~~~~~~        Each timer has its own 16-bit down counter, which is driven by the timer clock. When the down counter reaches zero, the timer interrupt request is generated to inform the CPU that the timer operation has been completed. When the timer counter reaches zero, the value of corresponding TCNTBn is automatically loaded into the down counter to continue the next operation. However, if the timer stops, for example, by clearing the timer enable bit of TCONn during the timer running mode, the value of TCNTBn will not be reloaded into the counter.

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         ~~~~~~~~        The value of TCMPBn is used for pulse width modulation (PWM). The timer control logic changes the output level when the down-counter value matches the value of the compare register in the timer control

The above is excerpted from the s3c2440 chip manual. This paragraph introduces the configuration of the timer peripherals in the s3c2440. From it, we can know:

There are 5 timers TIM0 ~ TIM4, except TIM4, all of them have PWM function.

TIM0 and TIM1 use the same 8-bit prescaler to divide PCLK as their clock. TIM2 ~ TIM4 use the same 8-bit prescaler to divide PCLK as their clock. Each TIM has a divider.

The timer counter TCNTBn stores the initial value loaded into the subtraction counter TCNTn, and the s3c2440 timer counts down. The timer compare register TCMPBn stores the initial value loaded into the compare register TCMPn.

Each timer has a 16-bit down counter TCNTn. When the counter value is equal to 0, an interrupt is triggered, and then the value of TCNTBn is loaded into the down counter.

TCMPBn is used in PWM mode.

Steps to configure the timer

TIMER INITIALIZATION USING MANUAL UPDATE BIT AND INVERTER BIT

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         ~~~~~~~~        An auto reload operation of the timer occurs when the down counter reaches 0. So, a starting value of the TCNTn has to be defined by the user in advance. In this case, the starting value has to be loaded by the manual update bit. The following steps describe how to start a timer:

Write the initial value into TCNTBn and TCMPBn.

Set the manual update bit of the corresponding timer. It is recommended that you configure the inverter on/off bit. (Whether use inverter or not).

Set start bit of the corresponding timer to start the timer (and clear the manual update bit).

If the timer is stopped by force, the TCNTn retains the counter value and is not reloaded from TCNTBn. If a new value has to be set, perform manual update.

First initialize TCNTBn and TCMPBn.

Set the manual update bit, update TCNTn and TCMPn, and then reset the manual update bit.

Turn on auto-reload and timer.