The structure and working principle of MCS-51 microcontroller

1. Basic composition of MCS-51 microcontroller

There are many kinds of MCS-51 single-chip microcomputer chips, such as 8051, 8031, 8751, 80c51, 80c31, etc. It consists of a central processing unit (CPU), clock circuit, program memory (ROM/EPROM), data memory (RAM), parallel I/O port (P0~P3), serial port, timer/counter and interrupt system. They are connected through a single bus and integrated on a semiconductor chip, that is, a single-chip microcomputer.

2. Internal structure and function of 8051 microcontroller

CPU

The central processing unit (CPU) is the core component inside the microcontroller. It determines the main functional characteristics of the microcontroller and consists of two parts: the arithmetic unit and the controller.

1. Calculator

The arithmetic unit is the computing part of the computer, which is used to implement arithmetic logic operations, bit variable processing, shifting and data transfer operations. It is composed of the arithmetic logic unit ALU as the core, plus the accumulator ACC, register B, temporary registers TMP1 and TMP2, program status word PSW, decimal adjustment circuit and Boolean processor specially used for bit operations.

(1) Arithmetic logic unit

The arithmetic logic unit ALU is used to complete the four operations of binary numbers and the logical operations of Boolean algebra. In addition, the judgment of the operation results affects the relevant flag bits of the program status flag register.

(2) Accumulator

The accumulator ACC is an 8-bit register and is the most frequently used register in the CPU. It can be used to store operands as well as intermediate results. The operands of most single-operand instructions in MCS-51 are taken from the accumulator ACC, and one operand in many double-operand instructions is also taken from the accumulator ACC. Most data operations in the microcontroller are performed through the accumulator ACC.

(3) Register B

Register B is an 8-bit register that is used by the ALU for multiplication and division operations. When executing a multiplication instruction, register B is used to store the high 8 bits of one of the multipliers and the product. When executing a division instruction, it is used to store the divisor and remainder. It can also be used as a general register.

(4) Program status word PSW

The program status word PSW is an 8-bit special function register, each bit of which contains the status information of the program running for the program to query and judge. The format and meaning of PSW are as follows:

1) Cy Carry flag. Cy is the most commonly used flag in PSW. It is set and cleared by hardware or software. It indicates whether there is a carry (borrow) in the operation result. If the operation result has a carry output (addition) or a borrow input (subtraction) in the highest bit, Cy is set to "1" by hardware; otherwise, Cy is set to "0".

2) AC Auxiliary (half) carry flag. When performing a subtraction operation, if the result of the operation produces a carry or borrow from the lower four bits to the upper four bits, it is set to "1" by hardware; otherwise it is cleared to "0".

3) F0 User flag bit. Defined and used by the user.

4) RS1 and RS0 are working register bank selection bits. The values ​​of these two bits determine which bank of registers is selected as the current register bank.

5)OV overflow flag.

6)Undefined.

7) P Parity flag. The P flag indicates the parity of the 1 number in ACC. After each instruction is executed, the microcontroller automatically sets or resets the P bit according to the content of ACC. If there is an odd number of 1s in the accumulator ACC, P=1; if there is an even number of 1s in the accumulator ACC, P=0.

(5) Boolean processor

2. Controller

The controller is the command and control component of the computer, which includes the program counter PC, instruction register IR, instruction decoder ID, data pointer DPTR, stack pointer SP, timing control and conditional transfer logic circuits, etc. It decodes the instructions from the memory, and sends out the control signals required for various operations at the specified time through the timing and control circuit, so that various components work in coordination to complete the operations specified by the instructions.

(1) Program Counter PC

PC is a 16-bit counter. In fact, PC is the byte address counter of the program memory. Its content is the address of the next instruction to be executed. The addressing range is up to 64k (216=65536=64k). PC has the function of automatically adding 1 to realize the sequential execution of the program. Its content can be changed by instructions such as transfer, call, return, etc. to realize the transfer of the program.

(2) Instruction decoder ID

When the instruction is taken out and sent to the instruction decoder ID through the instruction register IR, ID decodes the instruction, that is, converts the instruction into the required level signal. The CPU makes the timing control circuit generate various control signals required to execute the instruction according to the level signal output by ID, so that the computer can correctly execute various operations required by the program.

(3) Data pointer DPTR

The data pointer DPTR is a 16-bit register. Its function is to store a 16-bit address as the address for accessing the external program memory and the external data memory. When programming, DPTR can be used as a 16-bit register or as two 8-bit registers, that is, DPH is the high 8 bits of DPTR, and DPL is the low 8 bits of DPTR.

Storage System

The 8051 microcontroller adopts Harvard structure in system structure, and stores the program and data in two memories respectively. It is different from general-purpose computers that adopt von Neumann structure and share one memory for program and data. The memory of 8051 is physically divided into program memory (ROM) and data memory (RAM), and has four physically independent storage spaces, namely on-chip ROM and off-chip ROM, on-chip RAM and off-chip RAM.

From the user's perspective, the 8051 storage space is divided into three categories: 64k program memory address space with unified addressing 0000H~FFFFH inside and outside the chip; 256-byte data memory address space, address: 00H~FFH, 64k external data memory or I/O address space.

The above three address spaces overlap, that is, the lower 4k addresses of the program memory overlap; the data memory and the program memory all overlap; the lower 256 bytes of the data memory overlap. Although the addresses overlap, due to the use of different operating instructions and the selection of control signals EA and PSEN, there will be no confusion.

1. Program memory

The program memory is used to store program codes and constants, and is divided into two parts: on-chip ROM and off-chip ROM. The 8051 has a 4K ROM inside, with an address range of 0000H~0FFFH, and a 64K ROM outside the chip with a 16-bit address line. Both are uniformly addressed.

Whether the microcontroller fetches instructions from the internal ROM (EA=1) or the external ROM (EA=0) depends on the level of the CPU pin EA.

The 8051 executes instructions at the same speed when it fetches them from the on-chip ROM and the off-chip ROM.

There are some special locations in the program memory.

0000H~0002H System reset vector area

0003H~000AH INT0 interrupt address area

000BH~0012H T/C0 interrupt address area

0013H~001AH INT1 interrupt address area

001BH~0022H T/C1 interrupt address area

0023H~002AH Serial port interrupt address area

2. On-chip data memory

The data memory is used to store the intermediate results of the operation, flags, temporary storage and buffering of data, etc. It is divided into two parts: on-chip and off-chip. The on-chip data memory of 8051 is divided into the lower 128 (00H~7F) units and the upper 128 (80~FFH) units according to their functions.

3. Off-chip data storage

The off-chip data memory, namely the off-chip RAM, is generally composed of static RAM chips. Users can determine the capacity of the extended memory according to their needs. The MCS-51 microcontroller can access the off-chip RAM using the special function register - data pointer DPTR, with a maximum capacity of 64K.

The address range of the off-chip RAM is 0000H~FFFFH, where the 0000H~00FFH interval overlaps with the on-chip data storage space. The CPU uses MOV instructions and MOVX instructions to distinguish them.

3. Pin functions of MCS-51 microcontroller

The MCS-51 series microcontroller chips all have 40 pins. The pin functions are described as follows:

1. Power pins VSS and VCC

VSS is the voltage ground terminal, and VCC is the +5V power supply terminal.

2. Clock circuit pins XTAL1 and XTAL2

XTAL1 and XTAL2 are the external crystal oscillator lead terminals.

When the internal clock of the chip is used, these two pins are connected to a quartz crystal oscillator and a capacitor; when an external clock is used, they are used to connect an external pulse signal.

3. Control signal pins ALE, PSEN, EA and RST

（1）ALE/PROG

This pin is the address control latch control signal. When accessing external memory, ALE is used to latch the low 8 bits of the address appearing at port P0 to achieve isolation of the low address and data.

（2）PSEN

 This pin is the selection signal of the off-chip program memory, and the low level is effective. When reading instructions or constants from the off-chip ROM, each machine PSEN is valid twice to implement the read operation of the ROM unit. When accessing the off-chip RAM, the PSEN signal will not appear.

（3）EA/VPP

This pin is the control signal for accessing external program memory, and is valid at low level.

（4）RST/VPD

This pin is the reset signal, which is valid at high level. When this input terminal maintains a high level for more than 2 machine cycles, the microcontroller can be reset.

4. I/O (input, output) ports P0, P1, P2 and P3

(1) P0 port (P0.0~P0.7) P0 port is an open-drain 8-bit bidirectional I/O port, each bit can drive 8 LS-type TTL loads. When accessing off-chip memory, P0 provides the low 8-bit address line and 8-bit bidirectional data line in a time-sharing manner. When no off-chip memory is connected or the I/O is not expanded, P0 port can be used as a general input and output port. When P0 port is used as an input port, P0 port should first write "1" to the latch. At this time, all pins of P0 port are floating and can be used as high-impedance input. When P0 port is used as an output, since the output circuit is open-drain, an external pull-up resistor must be connected when driving the NMOS circuit.