How to configure NORFASH when using JLINK to download uboot to MINI2440?

Note: The following settings are applicable to downloading an empty board (i.e. no program in the chip) using JLINK, and are downloaded to NORFALSH.

1.Target Interface (as shown below):

2.CPU settings:

CPU settings include 3 parts:

2.1 Select CPU (S3C2440A is ARM920T core)

2.2 Set RAM address and size (S3C2440 has built-in RAM)

Using the on-chip RAM to assist in downloading the code will make it download very quickly, otherwise the download speed will be very slow.

2.3Init steps (here is to set the internal registers of the CPU. If the internal registers are not set initially, the download will fail)

As shown in the figure above, there are multiple data in the text file, which are write operations to the internal registers of the CPU to set the initial values ​​of the registers. Click "ADD" below to add commands. A total of 17 commands need to be added. The commands that need to be added are as follows:

     1- Disable MMU                                 

     2-Write 32bit           0x53000000    0x00000000          pWTCON,Watchdog disable

     3-Write 32bit           0x4A000008    0xFFFFFFFF        INTMSK,Disable interrupts

     4-Write 32bit           0x4A00001C    0xFFFFFFFF       INTSUBMSK,disable interrupts

     5-Write 32bit           0x48000000    0x22111120          Bus width & wait status

     6-Write 32bit           0x48000004    0x00000F40          Boot ROM control

     7-Write 32bit           0x48000008    0x00002E50          BANK1 control

     8-Write 32bit           0x4800000C    0x00002E50         BANK2 control

     9-Write 32bit           0x48000010    0x00002E50          BANK3 control

     10-Write 32bit          0x48000014    0x00002E50         BANK4 control

     11-Write 32bit          0x48000018    0x00002E50         BANK5 control

     12-Write 32bit          0x4800001C   0x00018005          BANK6 control

     13-Write 32bit          0x48000020    0x00018005          BANK7 control

     14-Write 32bit          0x48000024    0x00960542          DRAM/SDRAM refresh

     15-Write 32bit          0x48000028    0x00000032          Flexible Bank Size

     16-Write 32bit          0x4800002C    0x00000030         Mode register set for SDRAM

     17-Write 32bit          0x48000030    0x00000030          Mode register set for SDRAM

3. FLASH settings

Uncheck "Automatically detect" and select the NOR FLASH model manually. Select according to the NOR Flash on the development board. Here, select the SST39VF1601 model from SST manufacturer.

Conclusion:

After the above key settings, JLINK can download uboot to NOR FLASH to the development board. The following operations are to open uboot.bin: file->open data file; then connect the development board: Target->connect; burn uboot to norfalsh: Target->Program&Verify.