ATmega8 Interrupt Vectors

This section describes the interrupt handling of the ATmega8. For more general AVR interrupt handling, see P12 “Reset and Interrupt Handling”.

Notes: 
1. When the fuse bit BOOTRST is programmed, the program jumps to the Boot Loader after the MCU is reset.
2. When the IVSEL bit of the GICR register is set, the interrupt vector is transferred to the starting address of the Boot area. At this time, the actual address of each interrupt vector is the sum of the address in the table and the starting address of the Boot area.

Table 19 shows the location of reset and interrupt vectors under different BOOTRST/IVSEL settings. If the program never enables interrupts, the interrupt vector is meaningless. Users can write programs directly here. Similarly, if the reset vector is located in the application area and other interrupt vectors are located in the Boot area, the program can be written directly after the reset vector. The same is true in reverse.

Note: 
1. The reset address of the Boot area is listed in Table 82 on P 207. For the fuse bit BOOTRST, “1” means unprogrammed and “0” means programmed.

Typical reset and interrupt settings for ATmega8 are as follows:

When the fuse bit BOOTRST is not programmed, the Boot area is 2K bytes, and the IVSEL bit of the GICR register is set, the typical reset and interrupt settings are as follows:

When the fuse bit BOOTRST is programmed and the Boot area is 2K bytes, the typical reset and interrupt settings are as follows:

When the fuse bit BOOTRST is programmed, the Boot area is 2K bytes, and the IVSEL bit of the GICR register is set, the typical reset and interrupt settings are as follows:

Move interrupts between application and boot areas

The general interrupt control register determines the location of the interrupt vector table.

General Interrupt Control Register - GICR

• Bit 1 – IVSEL: Interrupt vector selection
When IVSEL is "0", the interrupt vector is located at the starting address of the Flash memory; when IVSEL is "1", the interrupt vector is transferred to the starting address of the Boot area. The actual starting address of the Boot area is determined by the fuse bit BOOTSZ. For details, please refer to P 196 "Support for boot loader - self-programming capability that can be read while writing (RWW, Read-While-Write)". In order to prevent unintentional changes to the interrupt vector table, the following process must be followed when modifying IVSEL:
1. Set the interrupt vector modification enable bit IVCE.
2. Write the required data to IVSEL in the next 4 clock cycles, and write "0" to IVCE at the same time.

Interrupts are automatically disabled when the above sequence is executed. In fact, interrupts are disabled when IVCE is set and remain disabled until the next statement after the IVSEL write operation. If there is no IVSEL write operation, interrupts remain disabled for 4 clock cycles after IVCE is set. It should be noted that although interrupts are automatically disabled, the value of bit I of the status register is not affected by this operation.

Note: If the interrupt vector is located in the Boot area and the Boot lock bit BLB02 is programmed, the interrupt is disabled when executing the program in the application area; if the interrupt vector is located in the application area and the Boot lock bit BLB12 is programmed, the interrupt is disabled when executing the program in the Boot area. For details on the Boot lock bit, see P 196 "Supporting Boot Loader - Read-While-Write Self-Programming Capability".

• Bit 0 – IVCE: Interrupt Vector Change Enable IVCE must be set when
changing IVSEL. IVCE is cleared by hardware 4 clock cycles after IVCE or IVSEL is written. As mentioned earlier, setting IVCE will disable interrupts. The code is as follows: