ARM Embedded System Development: Software Design and Optimization--Chapter 2 ARM Processor Basics

1. Register:

There are 37 registers in total, and up to 17 registers can be active (16 data registers, 2 status registers: CPSR and SPSR)

R13: Stack pointer: points to the top of the stack in the current processor mode

R14: Link register, saves the return address of the subroutine. [When the subroutine call instruction (BL) is executed, R14 can get the backup of R15 (program counter PC)]

R15: Programmer, the address of the next instruction to be fetched by the processor. [In ARM state, the instruction is 4-byte aligned, bit [1:0] is 0. Bit [31:2] stores PC]

[Note] R8-R12 of the fast interrupt are grouped registers, and each mode of R13-R14 has its own grouped register. R15 has no grouped register. User mode and system mode have no grouped registers.

2. Current Program Status Register CPSR:

3. Processor mode:

Except for user mode, each mode can be changed by rewriting the mode bit in cpsr. When an exception or interrupt occurs, the cpsr register is saved to the spsr register of the corresponding mode, but when the user program rewrites the cpsr register to switch modes, the cpsr is not automatically saved. System power-on: Start from management mode, ARM instruction state.

All except USR and SYS are abnormal modes

All modes except USR are privileged modes. The privileged mode can be switched to USR by directly modifying the corresponding bits in CPSR, but USR cannot modify CPSR directly, only through instructions.

The kernel state program of OS works in SVC mode, and the user state program works in USR mode.

The ARM CPU is in SVC mode when it is reset. After executing the startup code, it needs to switch to USR mode.

4. Thumb instructions

The operand of the instruction is still 32 bits, and the addressing address is still 32 bits.

In this state, when R15 (PC) bit 0 is read as 0, bits 31-1 store the address of the program counter. When writing to R15, bit 0 is ignored, and bits 31-1 store the value to be written to the program counter. That is, bit 0 of the PC remains 0, and the first 31 bits store the address of the next instruction.

ARM instructions: word alignment, the last two bits of the address are 0; thumb instructions: half-word alignment, the last bit of the address is 0. [Therefore, the last bit cannot be a useful address]

You can use the R0-R7 registers. Some instructions can also use the PC, lr, sp registers.

[Explanation]: BX jumps to . When the last bit is 0, it indicates the address of the thumb instruction. So the compiler automatically adds a state switch instruction and performs an AND operation with 0xfffffffe. Then it gets the real instruction address and copies it to the PC register.

[The addition operation is done by the compiler. The removal operation may be done automatically by the hardware and no instruction is generated]

Switching between arm and thumb

1. Switch from arm state to thumb state

　　The status register sets the lowest bit to 1

       BX instruction: R0[0]=1, then executing the BX R0 instruction will enter the thumb state

2. Switch from thumb state to ARM state

The lowest bit of the register is set to 0

BX instruction: R0[0]=0, then executing the BX R0 instruction will enter the arm state

When the processor performs exception handling, it starts execution from the exception vector address and automatically enters the ARM state.

Note: When the ARM processor starts executing code after reset, it is always in ARM state only;

Cortex-M3 only has Thumb-2 state and debug state;

Since Thumb-2 has 16-bit/32-bit instruction capabilities, there is no need for Thumb with Thumb-2.

In addition, ARM processors with Thumb-2 technology no longer need to switch between ARM state and Thumb-2 state because thumb-2 has 32-bit instruction capabilities.

In general, the essential difference between arm state and thumb state is the number of bits of instructions. arm is a 32-bit instruction state, while thumb is a 16-bit instruction state. The thumb-2 state is a combination and optimization of the arm state and thumb state.