ARM_Core processor mode and registers, structure talk

ARM processor working state: ARM processor has two working states. During the execution of the program, the processor can switch between the two working states without affecting the contents of the corresponding registers.

ARM state, when the processor executes 32-bit aligned ARM instructions; BX instruction, when the lowest bit of the operand register is 0, it enters the ARM state.

Thumb, the processor executes 16-bit aligned Thumb instructions. BX instruction, when the lowest bit of the operand register is 1, enters Thumb state.

BX (Branch Exchange): BX Rn; ##Rn can be any one of R0-R15. The instruction completes the jump of the 4Gbyte address space by copying the content of register Rn to the program counter PC.

After entering the abnormal interrupt, the ARM core will automatically switch to the ARM state, so the ARM instruction is at the entrance of the abnormal interrupt handler. If you need to switch to the Thumb state, you must switch to the ARM working state before returning from the abnormal interrupt. When the processor has an exception in the Thumb state, it will automatically switch to the Thumb state after returning.

ARM processors always start from the ARM working state.

ARM processor's 7 working modes:

USE mode: normal user mode.

FIQ mode: fast interrupt mode, supporting high-speed data transmission.

IRQ mode: normal interrupt mode.

SVC mode: Supervisor mode, operating system protection mode, handle software interrupt swi, reset.

ABT mode: data, instruction abort mode.

UND mode: undefined mode, supports software simulation.

SYS mode: System mode, running privileged operating system tasks.

The other 6 modes except user mode are called privileged modes. In privileged mode, the program can access all system resources and can switch the processor mode at will.

In user mode, some system resources protected by the operating system cannot be accessed, and processor modes cannot be switched directly. Exception handling is required by the application.

Among the privileged modes, the five modes except the system mode are called exception modes.

FIQ responds much faster than IRQ. First, FIQ has a higher priority. Second, ARM's FIQ has more registers of its own, which are automatically saved by ARM.

Exception handling process: store the next instruction in the LR register, assign CPSR to SPSR, force the CPSR run bit to be set, and jump to the exception handling function.

Return: Subtract the corresponding offset from the value in LR and send it to PC, and copy the value in SPSR to CPSR.

Exception vector table: 0x0000_0000---Reset, enter SVC mode.

                 0x0000_0004---Undefined instruction, enter UND mode.

                 0x0000_0008---Software interrupt, enter SVC mode.

                 0x0000_000C---Abort instruction and enter ABT mode.

                 0x0000_0010---Abort data and enter ABT mode.

                 0x0000_0014 --- Reserved

                 0x0000_0018---IRQ interrupt, enter IRQ mode.

                 0x0000_001C---FIQ interrupt, enter FIQ mode.

There are 37 registers in the ARM processor. There are 31 general registers: R0-R15, R13_svc, R14_svc, R13_abt, R14_abt, R13_und,

      R14_und, R13_irq, R14_irq, R8_frq----R14_frq.

                                            6 status registers: CPSR, SPSR_svc, SPSR_abt, SPSR_und, SPSR_irq, SPSR_fiq.

R13 is usually used as a stack pointer. R14 is usually used as a subroutine link.

CPSR is the current program status register. SPSR is the backup program status register.

31--28: NZCV (Negative Zero Carry Overflow)

27---8: Reserve

7----5: IFT (IRQ disable FIQ disable State bit)

4----0：Mode bits

0b10000---User mode, 0b10001---FIQ mode, 0b10010---IRQ mode, 0b10011---SVC mode, 0b10111---ABT mode,

0b11011---UND mode, 0b11111---SYS mode.

Question: Why does it switch the state according to the lowest bit of Rn? The lowest bit is 1, which means 8-bit alignment instead of 16-bit. Is arm itself aligned to 16-bit addresses? ?

ARM processor architecture development:

The arm system generally includes: mpcore, debug and trace, smmu, GIC, AMBA bus, security extension,

ARM supports up to 16 coprocessors, CP0-CP15, of which CP8-CP15 are reserved by ARM and CP0-CP7 are imp defined.

　　In the coprocessor model of arm, the coprocessor generally includes:

　　1) Primary and secondary coprocessor registers that make up the coprocessor interface;

　　2) internal registers;

In ARMv7 and earlier versions, the coprocessors included are:

　　1) CP15, which provides memory, cache, TCM control, and non-debug registers in the system; also known as the system control coprocessor

　　2) CP14, provides access to other system registers, including debug and trace;

　　3) CP10 and CP11 are used for SIMD and VFP control and need to be used at the same time.

ARM's coprocessor instructions include five:

　　1) CDP, coprocessor number operation instruction,

　　2) LDC, coprocessor data load instruction,

　　3) STC, coprocessor data storage instruction,

　　4) MCR, data transfer instruction from ARM register to coprocessor register,

　　5) MRC, data transfer instruction from coprocessor register to ARM register,

 Command format: