NXP LPC ARM must know knowledge

Registers and working modes:

7 working modes:
fiq/irq/abt/und/sys/usr/svc. Switching by "MSRcpsr_c,#0xdx". Entering svc mode at power-on.
The difference between svc and usr is: svc can be freely switched to any other mode by "MSR cpsr_c,#0xdx", but usr cannot.

Each mode has its own stack. After the program starts, you need to enter each mode in turn to set up your own stack, and finally enter the usr mode.

Many registers:
r0 - r7 (a1 - a4 / v1 - v4), r15 (pc) are visible in all modes.
r8 (v5), r9 (sb, v6), r10 (sl, v7), r11 (fp, v8), r12 (ip) have an independent mapping in fiq mode.
r13 (sp) / R14 (lr) use the same mapping in usr and sys modes, and have their own mapping in other modes.
cpsr is visible in all modes.
spsr is not mapped in usr and sys modes.

cpsr is a most special register, with the following structure:

31 30 29 28 27~8 7 6 5 4 3 2 1 0
N ZCV Reserved IFT M4 M3M2 M1 M0

Among them, N/Z/C/V are the flags of negative/zero/carry/overflow respectively. Read operation is possible in all modes.

I/F is the interrupt/fast interrupt disable bit, M4~M0 are the working mode control bits, and they are all inoperable in USR mode.

T is the Thum/ARM mode bit, which cannot be directly operated in all modes, otherwise there will be chaos. The pre-fetch error interrupt can capture this chaos. The state of Thum/ARM can only be switched by BX instruction.

In short, USR mode is very inconvenient. In this mode, the I/F bit can only be controlled by soft interrupts. The cpsr can only be operated by MSR/MRS instructions.

spsr in each working mode: When a mode switch caused by an emergency occurs, the spsr of the new mode automatically saves the value of the cpsr in preparation for restoring the cpsr when the mode is exited. When entering a mode under the control of the program, the cpsr will not be automatically saved to the corresponding spsr.

Prefetch Abort and Data Abort modes:
Prefetch Abort usually occurs after a self-modifying instruction. Data Abort occurs when an operand is taken from invalid memory, usually when the data pointer crosses the boundary. If the boundary is not specified in the scatter file, if the memory allocation exceeds the actual physical memory during compilation, DataAbort or Prefetch Abort will definitely occur.

Operations on special function registers:
There are usually two registers that operate the same special function. One is responsible for setting and the other is responsible for clearing. Such as VICIntEnable and VICIntEnClr, IOxSET and IOxCLR, etc. This makes it very easy to operate a certain bit or bits individually, such as: IO0SET = 0x00001100; IO0CLR = 0x00000011, etc., only changing a specific bit without affecting other bits. Of course, you can also use IO0PIN = 0x00001100 to directly set all bits.

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Memory map:
0-1G (0x0000, 0000 -0x3fff,ffff): On-chip Flash.
1-2G (0x4000, 0000 -0x7fff,ffff): On-chip RAM.
2-3.5G (0x8000, 0000 -0xbfff,ffff - 0xdfff,ffff): Off-chip memory.
3.5G - 3.75G (0xe000, 0000 - 0xefff,ffff): VPB peripherals.
3.75G - 4G (0xf000,0000 - 0xffff,ffff): AHB peripherals.

Although the addressing space of ARM7 is 4G, the LPC2200 series only provides a total of 16M addresses from A0 to A23. The chip select signals CS0 - CS3 are the decoded outputs of A24 and A25, dividing the off-chip storage area 0x8000,0000 - 0x83ff,ffff into bank0 - bank3, a total of 16M*4=64M. These 4 banks can be configured as 8/16/32-bit bus widths respectively. At reset, the bus width of bank0 is determined by the Boot1:0 pins, bank1 is 32 bits, bank2 is 16 bits, and bank3 is 8 bits.

The byte alignment signals (BLS0 - BLS3) coordinate the bus width and the data line width of the external memory chip.
When the memory is composed of "byte-width devices" (such as 62256) or "multi-byte devices that are not distinguished by bytes", RBLE should be set to "0". At this time, EMC pulls BLS0~BLS3 high during read access.
When the memory is composed of "16-bit or 32-bit devices with byte selection input", RBLE should be set to "1". At this time, EMC pulls BLS0~BLS3 low during read access.
Therefore, when the memory is composed of 62256, since "on-chip byte selection input" is not required, RBLE = '0' is set, and BLS0~BLS3 will only synchronize with nWR and can be used instead of nWR. However
, when the memory is composed of IS61LV25616AL, since the chip has "nLB" and "nUB" to control the low/high 8-bit input, RBLE = '1' is set, and BLS0~BLS3 will synchronize with both nRD and nWR. At this time, BLS0~BLS3 cannot be used to replace the nWR signal.

Address data bus: D0 - D31, A0 - A23, OE, WE, CS0 - CS3, BLS0 -BLS3
After startup, P2.7/P2.6 controls the boot mode, and then the program sets MEMMAP to determine the mapping of the interrupt vector.
BCFG0 - BCFG3 controls the read and write delay and bus width. Note the default value after reset.
PINSEL2 controls the pin function.

Boot Block
The BootBlock of LPC2114/2214 is solidified in the highest Flash block and is mapped to the area of ​​0x7FFF,E000 - 0x7FFFF,FFFF during operation. While LPC2210 does not have on-chip Flash, it has 8K on-chip ROM to store the BootBlock, which is also mapped to 0x7FFF,E000.
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VPB is only a bus used internally by ARM. It is connected to the AHB bus through a bridge and is transparent to the user. Therefore, you don't need to consider its existence, just know that 0xe000 - 0xffff,ffff is the address of the peripheral controller.

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VIC:
ARM has 19 interrupt sources, which are assigned VIC channels 0 to 18.
The vector control register VICVectCntl0-15 records the channel number and its enable bit.
When an interrupt occurs, a value in VICVectAddr0-15 will be copied to VICVectAddr.
If it is a non-vector interrupt, VICdefaultAddr is copied to VICVectAddr.
The program jumps to the address pointed to by VICVectorAddr.
When the interrupt returns, 0x00 is written to VICVectAddr.

Non-vector interrupts are those interrupts that are enabled (allowed) but not set in the corresponding VICVectorCntl0~15 and VICVectorAddr0~15.