MC9S12XS128 MAL BootLoader（2）

The user program can be written according to the normal program, but the following points should be noted

The program is written to a fixed location and cannot overlap with the location of the BootLoader program. Otherwise, the program may not be able to run after being downloaded by the BootLoader. The corresponding operations are also performed in prm.

If interrupts are needed, the interrupt vector should be offset;

Offset the starting vector;

Write address alignment.

1. The BootLoader program is written to a fixed location:

ROM_C000      = READ_ONLY   DATA_NEAR IBCC_NEAR  0xC000 TO   0xEFDF;

Make sure it does not overlap with the address starting from F000 of the BootLoader;

INTO  ROM_C000/*, ROM_4000*/;

2. Offset the interrupt vector. When an interrupt occurs, push the current PC position into the stack, and then find the current interrupt function through the interrupt vector. One interrupt vector cannot correspond to two interrupt function addresses.

To offset the interrupt vector, we must first define the following interrupt vector table, where unused interrupts are represented by Unimplemented_ISR, and then set the interrupt offset register IVBR = 0x7F in the main function.

3. The offset of the starting vector. The starting vector is the address that the PC pointer points to at the beginning of the program. The default value is FFFE. If it is offset, the program cannot be run directly and can only be run in the BootLoader. Therefore, when we use the host computer to send the S19 file of the program, we need to change the FFFE in the FFFE line to the address we need.

4. When using the host computer to transfer S19 files, some addresses are not aligned with the FLASH write operation address, such as FFFE, so we need to fill the data of FFF0~FFFD addresses with FF;

#pragma CODE_SEG NON_BANKED

interrupt void Unimplemented_ISR(void)

{

  asm BGND; //software breakpoint

}

#pragma CODE_SEG DEFAULT

typedef void (*near tIsrFunc)(void);

const tIsrFunc VectorTable[] @0xEF10 =

{

  Unimplemented_ISR,    // Vector base + 0x10   Spurious interrupt

  Unimplemented_ISR,    // Vector base + 0x12   System Call Interrupt (SYS)

  Unimplemented_ISR,    // Vector base + 0x14   Reserved

  Unimplemented_ISR,    // Vector base + 0x16   Reserved

  Unimplemented_ISR,    // Vector base + 0x18   Reserved

  Unimplemented_ISR,    // Vector base + 0x1A   Reserved

  Unimplemented_ISR,    // Vector base + 0x1C   Reserved

  Unimplemented_ISR,    // Vector base + 0x1E   Reserved

  Unimplemented_ISR,    // Vector base + 0x20   Reserved

  Unimplemented_ISR,    // Vector base + 0x22   Reserved

  Unimplemented_ISR,    // Vector base + 0x24   Reserved

  Unimplemented_ISR,    // Vector base + 0x26   Reserved

  Unimplemented_ISR,    // Vector base + 0x28   Reserved

  Unimplemented_ISR,    // Vector base + 0x2A   Reserved

  Unimplemented_ISR,    // Vector base + 0x2C   Reserved

  Unimplemented_ISR,    // Vector base + 0x2E   Reserved

  Unimplemented_ISR,    // Vector base + 0x30   Reserved

  Unimplemented_ISR,    // Vector base + 0x32   Reserved

  Unimplemented_ISR,    // Vector base + 0x34   Reserved

  Unimplemented_ISR,    // Vector base + 0x36   Reserved

  Unimplemented_ISR,    // Vector base + 0x38   Reserved

  Unimplemented_ISR,    // Vector base + 0x3A   Reserved

  Unimplemented_ISR,    // Vector base + 0x3C   Reserved

  Unimplemented_ISR,    // Vector base + 0x3E   ATD0 Compare Interrupt

  Unimplemented_ISR,    // Vector base + 0x40   Reserved

  Unimplemented_ISR,    // Vector base + 0x42   Reserved

  Unimplemented_ISR,    // Vector base + 0x44   Reserved

  Unimplemented_ISR,    // Vector base + 0x46   Reserved

  Unimplemented_ISR,    // Vector base + 0x48   Reserved

  Unimplemented_ISR,    // Vector base + 0x4A   Reserved

  Unimplemented_ISR,    // Vector base + 0x4C   Reserved

  Unimplemented_ISR,    // Vector base + 0x4E   Reserved

  Unimplemented_ISR,    // Vector base + 0x50   Reserved

  Unimplemented_ISR,    // Vector base + 0x52   Reserved

  Unimplemented_ISR,    // Vector base + 0x54   Reserved

  Unimplemented_ISR,    // Vector base + 0x56   Reserved

  Unimplemented_ISR,    // Vector base + 0x58   Reserved

  Unimplemented_ISR,    // Vector base + 0x5A   Reserved

  Unimplemented_ISR,    // Vector base + 0x5C   Reserved

  Unimplemented_ISR,    // Vector base + 0x5E   Reserved

  Unimplemented_ISR,    // Vector base + 0x60   Reserved

  Unimplemented_ISR,    // Vector base + 0x62   Reserved

  Unimplemented_ISR,    // Vector base + 0x64   Reserved

  Unimplemented_ISR,    // Vector base + 0x66   Reserved

  Unimplemented_ISR,    // Vector base + 0x68   Reserved

  Unimplemented_ISR,    // Vector base + 0x6A   Reserved

  Unimplemented_ISR,    // Vector base + 0x6C   Reserved

  Unimplemented_ISR,    // Vector base + 0x6E   Reserved

  Unimplemented_ISR,    // Vector base + 0x70   Reserved

  Unimplemented_ISR,    // Vector base + 0x72   Reserved

  Unimplemented_ISR,    // Vector base + 0x74   Periodic interrupt timer channel 3

  Unimplemented_ISR,    // Vector base + 0x76   Periodic interrupt timer channel 2

  Unimplemented_ISR,    // Vector base + 0x78   Periodic interrupt timer channel 1

  PIT0_ISR,             // Vector base + 0x7A   Periodic interrupt timer channel 0

  Unimplemented_ISR,    // Vector base + 0x7C   High Temperature Interrupt (HTI)

  Unimplemented_ISR,    // Vector base + 0x7E   Autonomous periodical interrupt (API)

  Unimplemented_ISR,    // Vector base + 0x80   Low-voltage interrupt (LVI)

  Unimplemented_ISR,    // Vector base + 0x82   Reserved

  Unimplemented_ISR,    // Vector base + 0x84   Reserved

  Unimplemented_ISR,    // Vector base + 0x86   Reserved

  Unimplemented_ISR,    // Vector base + 0x88   Reserved

  Unimplemented_ISR,    // Vector base + 0x8A   Reserved

  Unimplemented_ISR,    // Vector base + 0x8C   PWM emergency shutdown

  Unimplemented_ISR,    // Vector base + 0x8E   Port P Interrupt

  Unimplemented_ISR,    // Vector base + 0x90   Reserved

  Unimplemented_ISR,    // Vector base + 0x92   Reserved

  Unimplemented_ISR,    // Vector base + 0x94   Reserved

  Unimplemented_ISR,    // Vector base + 0x96   Reserved

  Unimplemented_ISR,    // Vector base + 0x98   Reserved

  Unimplemented_ISR,    // Vector base + 0x9A   Reserved

  Unimplemented_ISR,    // Vector base + 0x9C   Reserved

  Unimplemented_ISR,    // Vector base + 0x9E   Reserved

  Unimplemented_ISR,    // Vector base + 0xA0   Reserved

  Unimplemented_ISR,    // Vector base + 0xA2   Reserved

  Unimplemented_ISR,    // Vector base + 0xA4   Reserved

  Unimplemented_ISR,    // Vector base + 0xA6   Reserved

  Unimplemented_ISR,    // Vector base + 0xA8   Reserved

  Unimplemented_ISR,    // Vector base + 0xAA   Reserved

  Unimplemented_ISR,    // Vector base + 0xAC   Reserved

  Unimplemented_ISR,    // Vector base + 0xAE   Reserved

  Unimplemented_ISR,    // Vector base + 0xB0   CAN0 transmit

  Unimplemented_ISR,    // Vector base + 0xB2   CAN0 receive

  Unimplemented_ISR,    // Vector base + 0xB4   CAN0 errors

  Unimplemented_ISR,    // Vector base + 0xB6   CAN0 wake-up

  Unimplemented_ISR,    // Vector base + 0xB8   FLASH

  Unimplemented_ISR,    // Vector base + 0xBA   FLASH Fault Detect

  Unimplemented_ISR,    // Vector base + 0xBC   Reserved

  Unimplemented_ISR,    // Vector base + 0xBE   Reserved

  Unimplemented_ISR,    // Vector base + 0xC0   Reserved

  Unimplemented_ISR,    // Vector base + 0xC2   Reserved

  Unimplemented_ISR,    // Vector base + 0xC4   CRG self-clock mode

  Unimplemented_ISR,    // Vector base + 0xC6   CRG PLL lock

  Unimplemented_ISR,    // Vector base + 0xC8   Reserved

  Unimplemented_ISR,    // Vector base + 0xCA   Reserved

  Unimplemented_ISR,    // Vector base + 0xCC   Port H

  Unimplemented_ISR,    // Vector base + 0xCE   Port J

  Unimplemented_ISR,    // Vector base + 0xD0   Reserved

  Unimplemented_ISR,    // Vector base + 0xD2   ATD0

  Unimplemented_ISR,    // Vector base + 0xD4   SCI1

  Unimplemented_ISR,    // Vector base + 0xD6   SCI0    

  Unimplemented_ISR,    // Vector base + 0xD8   SPI0    

  Unimplemented_ISR,    // Vector base + 0xDA   TIM Pulse accumulator input edge     

  Unimplemented_ISR,    // Vector base + 0xDC   TIM Pulse accumulator A overflow     

  Unimplemented_ISR,    // Vector base + 0xDE   TIM timer overflow     

  Unimplemented_ISR,    // Vector base + 0xE0   TIM timer channel 7     

  Unimplemented_ISR,    // Vector base + 0xE2   TIM timer channel 6     

  Unimplemented_ISR,    // Vector base + 0xE4   TIM timer channel 5     

  Unimplemented_ISR,    // Vector base + 0xE6   TIM timer channel 4     

  Unimplemented_ISR,    // Vector base + 0xE8   TIM timer channel 3     

  Unimplemented_ISR,    // Vector base + 0xEA   TIM timer channel 2     

  Unimplemented_ISR,    // Vector base + 0xEC   TIM timer channel 1     

  Unimplemented_ISR,    // Vector base + 0xEE   TIM timer channel 0     

   RTI_ISR,    // Vector base + 0xF0   Real time interrupt

  Unimplemented_ISR,    // Vector base + 0xF2   IRQ     

  Unimplemented_ISR,    // Vector base + 0xF4   XIRQ     

  Unimplemented_ISR,    // Vector base + 0xF6   SWI     

  Unimplemented_ISR     // Vector base + 0xF8   Unimplemented instruction trap     

};