Problems with S3C2440 booting from NAND Flash and NOR FLASH

1. Why can't NAND FLASH run programs directly?

    NAND FLASH itself is connected to the controller instead of the system bus. The CPU operation mechanism is: after the CPU starts, it needs to fetch instructions for execution. If it is SROM, NOR FLASH, etc., the CPU can fetch instructions and execute them by sending an address through the address line. NAND FLASH cannot do this because NAND FLASH uses pin multiplexing and has its own set of timings. In this way, the CPU cannot fetch executable code and cannot initialize the system.

    NAND FLASH is a sequential access device and cannot be accessed randomly, so the program cannot branch or jump. So how do you design a program?

    U-BOOT supports processors of various architectures such as ARM and PowerPC, and also supports various operating systems such as Linux, NetBSD and VxWorks. It is mainly used to develop bootloaders, the initialization code for embedded systems. Bootloader is a piece of code that is executed after the chip is reset and before entering the operating system. It completes the transition from hardware startup to operating system startup and provides a basic operating environment for running the operating system, such as initializing the CPU, stack, and memory system. Its function is similar to the BIOS of a PC.

2. Why can s3c2440 boot from NAND FLASH?

    It is understood that NOR FLASH has small capacity, fast speed, good stability, and is suitable for program storage.

    NAND FLASH has a large total capacity and is suitable for data storage. It cannot be started from NAND FLASH. The read and write timing of NAND FLASH cannot be directly generated by ARM hardware. To read and write NAND FLASH, it must be implemented through a program. It is obvious that NAND FLASH has only 8 data and address multiplexing data address interfaces. 2410/2440 can be started directly from NAND FLASH because it maps the first 4K of NAND to the RAM space.

2.1 Flash Types

    NOR FLASH address lines and data lines are separated. When the address and control signals come in, the data comes out.

    NAND Flash address lines and data lines are together and need to be controlled by a program to output data.

    In layman's terms, it is not enough to just give the address, you need to give the command first, then the address, to read the NAND data. And all of this is done on one bus.

    Conclusion: ARM cannot boot directly from NAND. NAND Flash can only be used after the program is loaded.
The program can only be loaded from mask rom or Nor flash.

    Samsung's 2410 can boot the program from NAND FLASH. It will copy the first 4KB of the first block to the internal SRAM and then execute it from the SRAM. In other words, you need to write a boot program less than 4K in length, which is used to copy the main program to SDRAM for execution (NAND FLASH address is not linear, the program cannot be run directly, it must be copied to linear RAM)

3.NAND boot and NOR boot:

    The hardware startup mode needs to be detected. The startup mode is determined by the hardware OM0 pin. The software cannot detect the hardware level status, but it can be detected based on the CPU startup characteristics.

3.1 NAND boot:

    If configured to boot from NAND FLASH (the boot mode selection switch is pulled to the nand end, and the OM0 pin is pulled low), the NAND controller of S3C2440 will automatically move the first 4K code data in NAND FLASH to the internal SRAM (address 0x40000000), and also map the SRAM address to the address 0x00000000. The CPU starts running the program from the position 0x00000000. [When the CPU is started from NAND FLASH, the CPU will copy the 4KB data starting from NAND FLASH to the 4KB internal RAM called "Steppingstone" (starting address 0) through the internal hardware, and then jump to address 0 to start execution]

3.2 NOR boot:

    If it is configured to start from NOR FLASH (the start mode selection switch is pulled to the NOR end, and the OM0 pin is pulled high), 0x00000000 is the actual starting address of NOR FLASH. The program in NOR FLASH starts running from here, and data copying and address mapping are not involved.

3.3 Summary:

    When NAND is started, address 0x00000000 is the address mapped by the internal SRAM;

     When NOR is started, the address 0x00000000 is the actual starting address of NOR FLASH. Writing data to NOR FLASH requires a specific command sequence, while writing data to the memory can directly assign values ​​to the memory address.

     For the S3C2440 processor, when M[1:0] selects 01 or 10: the norflash base address is 0x00000000, and the SRAM top address is 0x40000FFF. After power-on, the processor directly fetches instructions from 0x00000000, and the SP (stack pointer register) of the arm processor points to 0x40000FFF.

    OM[1:0] selects 00, S3C2440 will enable the internal SRAM buffer and automatically copy the first 4KB of the program in nandflash to BootSRAM. The base address of BootSRAM is 0x00000000, and the top address is 0x00000FFF. After power-on, the arm processor takes the first instruction from 0x00000000, and the SP (stack pointer register) of the arm processor points to 0x00000FFF.

4. The basic principle of starting U-BOOT from Nand Flash

4.1 Pre-4K Issues

    If the S3C2410 is configured to boot from Nand Flash (configuration is set by hardware engineers on the circuit board), the Nand Flash controller of the S3C2410 has a special function. After the S3C2410 is powered on, the Nand Flash controller will automatically move the first 4K data on the Nand Flash to the 4K internal RAM, and set 0x00000000 as the starting address of the internal RAM. The CPU starts from the 0x00000000 position of the internal RAM. This process does not require program intervention. The work that the programmer needs to complete is to put the most core startup program in the first 4K of Nand Flash.

4.2 What to do if the program size is larger than 4K?

    Then when the program is larger than 4k, when we boot with nand flash, the first 4kb is copied to the on-chip RAM for execution (automatically completed). We initialize SDRAM in the first 4k program (SDRAM needs to be initialized before use), and then copy the rest of the program to SDRAM (isn't it only 4kb that is copied to the on-chip RAM for execution) and then jump to SDRAM to execute the rest of the program.

     That is to say, usually when the program is larger than 4kb, we need to copy the program to SDRAM to run. (If the program is smaller than 4KB, then there is no need to copy it. After booting in nand flash mode, the program is copied to the 4kb RAM on the chip to run.)

    Well, since the program needs to be copied from NAND flash to SDRAM to run when it is larger than 4kb, it is natural to think that the first part of the program burned into NAND flash should be to initialize SDRAM (the program needs to be copied to SDRAM to run in the end) and copy the rest of the program in NAND flash to SDRAM (it is OK to copy all of it, it is more convenient), and then jump to SDRAM for execution.

4.2 Arrangements for the start-up procedure

    Since the code that the Nand Flash controller moves from the Nand Flash to the internal RAM is limited, we must complete the S3C2410 core configuration and move the rest of the boot code (U-BOOT) to RAM in the first 4K of the boot code.

     The u-boot source code does not support booting from nand flash, but s3c2410 supports booting from nand flash. After the development board (sbc-2410x) is powered on, s3c2410 copies the first 4k of nand flash (which stores some functions of u-boot - copy function - copy the contents of nand flash to SDRAM) to sram (sram inside the s3c2410 chip). This requires modifying the u-boot source code and adding u-boot functions: enable u-boot to copy itself to the SDRAM on the development board after obtaining execution rights, so that the processor can execute u-boot.

    The commands, addresses, and data of Nand Flash are all sent through the I/O port, and the pins are multiplexed. The advantage of this is that the number of NAND FLASH pins can be significantly reduced. In the future, if the designer wants to replace NAND FLASH with a higher density and larger capacity, there is no need to change the circuit board.

5. Why does NOR boot set sp to 0x40000000+4096

    When booting with NOR, the 8 BANKs BANK0-BANK7 of the storage controller on the chip correspond to other uses, so the designer uses the address 0x40000000 at the end of BANK7 as the startup address of NOR FLASH, and the startup address of NAND FLASH is 0x00000000.

    Because for the startup file .S, 4K space is enough to store the code segment, BSS... and stack segment. Because the SP of the stack moves from high address to low address, the starting address of the stack should be placed at the high address of the stack segment.

    You don't have to set it to 4096, but make sure the stack length does not overlap with other segments below. If it overlaps, a bug will occur. The insurance value is 4096 (4K, see the figure above) because SRAM is designed to be 4K.