Design and implementation of an I2C device control method

1 Introduction

I2C (Inter-Integrated Circuit) bus is a two-wire serial bus developed by PHILIPS, which is used to connect microcontrollers and their peripherals. It is a bus standard widely used in the field of microelectronic communication control. It is a special form of synchronous communication, with the advantages of few interface lines, simple control method, small device package, and high communication rate. AT91SAM7X256 is an industrial-grade chip based on ARM7 launched by Atmel in 2005. It is valued by developers in the embedded field for its small size, low power consumption, wide connection methods, rich processing resources, and flexible control. This article introduces the use of the TWI interface (two-wired interface) of the I2C controller of AT91SAM7X256, and takes the I2C device E2PROM and calendar clock chip as examples to realize the reading and storage of time data by AT91SAM7X256. At the same time, in order to verify whether the reading and storage of time data are correct, the data in E2PROM is read to the memory for inspection using the online emulator J-LINK of AT91SAM7X256.

ARM (Advanced RISC Machines) is a well-known company in the microprocessor industry. It has designed a large number of high-performance, low-cost, low-energy RISC processors, related technologies and software. The technology has the characteristics of high performance, low cost and low energy consumption. It is suitable for a variety of fields, such as embedded control, consumer/educational multimedia, DSP and mobile applications. ARM (Advanced RISC Machines) is a well-known company in the microprocessor industry. It has designed a large number of high-performance, low-cost, low-energy RISC processors, related technologies and software. The technology has the characteristics of high performance, low cost and low energy consumption. It is suitable for a variety of fields, such as embedded control, consumer/educational multimedia, DSP and mobile applications.

2 Hardware Design

2.1 Hardware module structure

The hardware module structure of the circuit is shown in Figure 1.

The TWI interface of AT91SAM7X256 consists of a clock line TWCK and a data line TWD, and the generated signal timing complies with the I2C bus specification; PCF8563 is an industrial-grade clock chip with I2C bus interface function launched by Philips; AT24C08 is a two-wire serial port E2PROM launched by Atmel that complies with the I2C specification. The TWCK and TWD of AT91SAM7X256 are connected to the SCL and SDA of the chip PCF8563 and AT24C08 respectively, and the CPU reads and stores the time data through the TWI interface. In order to ensure that the CPU does not conflict with the PCF8563 and AT24C08, this article connects the A2 pin of AT24C08 to a high level. Since the I2C bus is at a high level when idle, in order to realize the "wired AND" function, the devices connected to the bus are all open collectors, so the bus needs an external pull-up resistor R. The TWI of AT91SAM7X256 has two working modes: master and slave. In this article, AT91SAM7X256 is the controller and should work in master mode.

2.2 TWI interface of AT91SAM7X256

The TWD and TWCK pins of AT91SAM7X256 are multiplexed with the I/O pins of the device. At the same time, AT91SAM7X256 adopts a power-saving solution that controls functional units individually. The power management unit PMC controls whether the clocks of each functional unit are working. Therefore, to use the TWI interface, you need to first configure TWD and TWCK to the peripheral connection and open circuit state, and then configure PMC to make the TWI clock in working state.

The TWI interface can provide a transmission rate of up to 400 kb/s. In order to adapt the data transmission rate to different applications, the signal frequency of TWCK can be adjusted by configuring the control register TWI_CWEG of the clock pulse generator.

The signal timing generated by the TWI interface complies with the I2C bus specification. When reading/writing 1 byte of data, the master device needs to provide the slave device's device address, internal address, read/write control, and start and stop flags. In the process of sending and receiving data, the control register TWI_CR, the master mode register TWI_MMR, the internal address register TWI_IADR, the status register TWI_SR, the transmission holding register TWI_THR, and the receiving holding register TWI_RHR are mainly used. The slave device address is set in TWI_MMR, and the internal address of the slave device is set in TWI_IADR; whether to send the start signal and stop signal is set in TWI_CR; NAK (no response), OVER (operation error), TXRDY (send ready), RXRDY (receive ready), TX-COMP (transmission complete) and other status bits are obtained by querying WI_SR.

The process of writing data includes: after TWI_THR writes data, the CPU generates a start signal to start transmission, the data in TWI_THR is transmitted by TWD after parallel-to-serial conversion, and when the CPU receives the response signal from the slave device, the TXRDY bit of TWI_SR will automatically set to "1", indicating that the data has been written to the slave device. The process of reading data includes: after the CPU sends a start signal, if the RXRDY bit of TWI_SR is "1", it means that there is data waiting to be received in TWI_RHR. When the data in TWI_RHR is read out, RXRDY is automatically set to "0". When the reading/writing of data is completed, the CPU will generate a stop signal to end the transmission, and the TXCOMP of TWI_SR will automatically set to "1".

2.3 How to use the PCF8563 calendar clock chip

According to the I2C protocol, PCF8563 has a unique device address of 0A2H. This article focuses on the reading method of the hour, minute and second data of PCF8563. The internal registers used here include control/status register 1 (address 00H), second register (address 02H), minute register (address 03H), and hour register (address 04H). Since the hour, minute and second data are stored in the register in BCD format, the high bits of each time register are invalid.

To make PCF8563 work in normal mode, it is necessary to set the control/status register 1 to 00H. At the same time, in order to store the correct time data, it is necessary to mask the invalid high bits in the read data. If you need to calibrate the time, you only need to write the hour, minute, and second registers.

2.4 How to use AT24C08

AT24C08 is an E2PROM with a capacity of 8192 b (1024 B). AT24C08 is divided into 4 pages, each page has 256 bytes, so if you want to access a unit, you need 10 bits for addressing, of which the highest two bits are the page address and the lower 8 bits are the address within the page. The definition of the device address is shown in Figure 2, where P1P0 corresponds to the page address, and pin A2 can set two sets of device addresses for AT24C08. When A2 is low, the device addresses of the 4 pages are 0A0H, 0A2H, 0A4H, and 0A6H respectively; when A2 is high; otherwise, they are 0A8H, 0AAH, 0ACH, and 0AEH. Therefore, in order to avoid device address conflicts between AT24C08 and PCF8563, A2 needs to be connected to a high level.

The write operation of AT24C08 supports two modes: "byte write" and "page write". In the "byte write" mode, the master device needs to provide a start signal, device address, internal address and stop signal for each byte written; the "page write" mode is to write data continuously, and the master device needs to provide a start flag, device address and internal address, and send a stop flag after all the data are written.

The read operation of AT24C08 supports three modes: "current address read", "random read" and "sequential read". "Current address read" means reading 1 byte from the current internal address unit, so the master device only needs to provide the start signal, device address and stop signal; "random read" means reading 1 byte from any internal address unit, so the master device needs to provide a start signal, device address, write operation, device internal address and stop signal, set the internal address of the device, and then read the data in the "current address read" mode; "sequential read" means reading multiple bytes continuously from the current address, so the master device needs to provide the start signal, device address, read operation, and send a stop signal after all the data are read.

In order to quickly read and write data, this article uses page write to write data to AT24C08; and uses a combination of "random read" and "sequential read" to read AT24C08 data.

3 Software Design

3.1 Design of TWI initialization program

According to the functional characteristics of TWI, the initialization of TWI includes the following 4 steps:

(1) Configure the PIO controller so that the multiplexed pin drives the TWI signal;

(2) Configure PMC to put the TWI clock in working state;

(3) Configure TWI to work in master mode. In this paper, the CPU is the master device, and the calendar and storage chip are slave devices;

(4) Set the data transmission rate and configure the TWI clock waveform generator register.

3.2 Design of PCF8563 driver

In order to control the working mode of PCF8563, it is necessary to write control words to it; in order to obtain the time information output by PCF8563, it is necessary to perform a read operation on it. The process of reading/writing data is shown in Figure 3.

This article designs and writes the following read and write functions:

Among them, pTwi is a structure pointer, which points to a structure storing TWI registers. Each TWI register can be accessed through pTwi; address represents the device address; im_address represents the internal address of the device; data represents the variable pointer for reading and writing data.

Therefore, if PCF8563 is operated in normal mode and the "time" data is read, the following code can be used:

3.3 Design of AT24C08 Driver

Since AT24C08 consists of 4 pages with different device addresses and uses a continuous read and write data operation mode, the reading and writing of AT24C08 and PCF8563 have the following differences.