Quickly learn Arm (23)--lpc2300 system clock 2

Continuing from the previous article, let's take a look at the PLL setup steps:

1. If the PLL is already connected, we disconnect it first by using a feed sequence to disconnect the PLL. The feed sequence is of course implemented by writing the feed register PLLFEED. The feed sequence mechanism is used to prevent the relevant parameters of the PLL from being accidentally modified. The LPC2300 series ARM provides hardware protection. Only by writing 0xAA to the PLL feed register first and then writing 0x55, the relevant parameters of the PLL can be effectively changed.

2. Disable the PLL with a feed sequence, that is, stop the operation of the flow-controlled oscillator CCO.

3. Select the PLL input clock source through the clock source selection register CLKSRCSEL.

4. Write the PLL configuration register PLLCFG and use a feed sequence to make it effective. The PLL configuration register is only valid when the PLL is disabled.

5. Send another feed sequence to enable the PLL (to restart the stopped current-controlled oscillator CCO)

6. After the PLL is locked, that is, stable, connect the PLL with a feed sequence.

Note: The PLL will be turned off and switched out of the clock system during chip reset and financial power-down mode. After the chip wakes up from power-down mode, the program must reinitialize the PLL, activate the PLL and wait for it to lock before connecting to the PLL.

There are four registers associated with PLL, three of which are control registers and one is a status register.

PLL Control Register (PLLCON): A register that stores updated PLL control bits. Values ​​written to this register take effect only after a valid PLL feed sequence is sent.

PLL Configuration Register (PLLCFG): This register stores updated PLL configurations. Values ​​written to this register take effect only after a valid PLL feed sequence occurs.

PLL Status Register (PLLSTAT): A read-back register for PLL control and configuration information. If a write operation is performed to the PLL control register or the PLL configuration register, but no PLL feed sequence is generated, these values ​​will not reflect the current state of the PLL.

PLL Feed Register (PLLFEED): This register enables loading of PLL control and configuration information from the PLL control register and PLL configuration register into the image register that affects the operation of the PLL.

The following code is copied by me. Its main function is to select the 4MHz internal oscillator as the PLL clock, so that the input clock is increased to 288MHz. The process is as follows:

Select clock source --> Enable PLL --> Set division value --> PLL feed sequence --> Wait for PLL to be available --> Set CPU division value --> Connect PLL --> PLL feed sequence --> Wait for PLL to lock. The code is as follows:

   CLKSRCSEL   =0x01;

   PLLCON      =1;

   PLLCFG       =0<<16;

   PLLCFG      |=35;

   PLLFEED     =0xAA;

   PLLFEED     =0x55;

   while(((PLLSTAT & (1<<24))=0));

   CCLKCFT     =3;

   PLLCON      =3;

   PLLFEED     =0xAA;

   PLLFEED     =0x55;

   while(((PLLSTAT & (3<<25))!=(3<<25>>>;

     ......

Please note that the storage values ​​corresponding to the PLLCFG above are N-1=0, M-1=35. So N=1, M=36. Please pay attention to this point.