TQ210 —— s5pv210 start.S analysis

/*

 *  armboot - Startup Code for S5PC110/ARM-Cortex CPU-core

 *

 *  Copyright (c) 2009 Samsung Electronics

 *

 *

 * See file CREDITS for list of people who contributed to this

 * project.

 *

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License as

 * published by the Free Software Foundation; either version 2 of

 * the License, or (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,

 * MA 02111-1307 USA

 *

 * Base codes by scsuh (sc.suh)

 */

/*

 *  mod by lhh

 *

 *  Our U-Boot Memory Map with static mmu_table

 *                                      (offset)

 *       --------------------------     

 *       |     Stack     (512KB)  |

 *       --------------------------     

 *       |     Heap       (1MB+envsize)   |

 *       --------------------------    

 *       |     IRQ Stack  (KB)   | <------------------------ if exists

 *       --------------------------     

 *       |     FIQ Stack  (KB)   | <------------------------ if exists

 *       --------------------------     

 *       |     GBL       (B)   |

 *       --------------------------     0x03exxxxx

 *       |     BSS and Reserved   |

 *       --------------------------     0x03e60000

 *       |     U-Boot    (512KB)  |

 *       --------------------------     0x03e00000

 */

#include

#include

#if defined(CONFIG_ENABLE_MMU)

#include

#endif

#include

#ifndef CONFIG_ENABLE_MMU

#ifndef CFG_PHY_UBOOT_BASE

#define CFG_PHY_UBOOT_BASE CFG_UBOOT_BASE

#endif /* CFG_PHY_UBOOT_BASE */

#endif /* CONFIG_ENABLE_MMU */

/*

 *************************************************************************

 *

 * Jump vector table as in table 3.1 in [1]

 *

 *************************************************************************

 */

#if defined(CONFIG_EVT1) && !defined(CONFIG_FUSED)

.word 0x2000

.word 0x0

.word 0x0

.word 0x0

#endif

 /******************************************************************************

 * .global keyword, equivalent to C language extern, global variable, externally accessible

 * _start program entry, that is, the beginning of the uboot code. The ":" label after _start is similar to the label after goto in C.

 * The value of _start is the very beginning of the code, relative to 0; jump to the reset label to execute, that is, reset vector

 * After ARM is powered on and reset, it executes from 0x00000000 and jumps to reset. The exception vector table will not be executed.

 *

 * Exception vector table: undefined instruction exception, soft interrupt exception, preprocessing instruction exception, unused, data exception,

 * Interrupt exception, fast interrupt exception; each occupies one byte, the address range is 0x0000 0000 ~ 0x0000 0020

 * The purpose of setting the exception vector table is to identify the bootloader. Whenever an exception occurs in the system,

 * The CPU will look up the table from 0x00000000 in memory and do the corresponding processing according to the exception number

*******************************************************************************/

.globl _start

_start: b reset @Relative jump, absolute jump cannot be used because the startup code may still be running in IRAM (SRAM inside s5pv210)

ldr pc, _undefined_instruction

ldr pc, _software_interrupt

ldr pc, _prefetch_abort

ldr pc, _data_abort

ldr pc, _not_used

ldr pc, _irq

ldr pc, _fiq

@ .word pseudo-operation, which allocates a word (4 bytes) of memory units

@ In C: pc = *(_x) = x x = exception vector

_undefined_instruction:

.word undefined_instruction

_software_interrupt:

.word software_interrupt

_prefetch_abort:

.word prefetch_abort

_data_abort:

.word data_abort

_not_used:

.word not_used

_irq:

.word irq

_fiq:

.word fiq

_pad:

@ This is just an initial value, fill 4 bytes

.word 0x12345678 /* now 16*4=64 */

.global _end_vect @ exception vector end label

_end_vect:

@ means the following code uses 16-byte alignment, and the missing characters are filled with 0xdeadbeef (bad beef)

@ There is also a similar bad code 0xbadc0de (haha), there is no o in hexadecimal, it is the number 0

.balignl 16,0xdeadbeef

/*

 *************************************************************************

 *

 * Startup Code (reset vector)

 *

 * do important init only if we don't start from memory!

 * setup Memory and board specific bits prior to relocation.

 * relocate armboot to ram

 * setup stack

 *

 *************************************************************************

 */

@ Code segment base address, defined in boardsamsungTQ210config.mk, TEXT_BASE=0x23e00000

_TEXT_BASE:

.word TEXT_BASE

/*

 * Below variable is very important because we use MMU in U-Boot.

 * Without it, we cannot run code correctly before MMU is ON.

 * by scsuh.

 */

_TEXT_PHY_BASE:

.word CFG_PHY_UBOOT_BASE

@ *(_armboot_start) = _start

.globl _armboot_start

_armboot_start:

.word _start

/*

 * These are defined in the board-specific linker script.

 */

 @ The stack header and stack footer are defined in the link script: boardsamsungTQ210u-boot.lds

.globl _bss_start

_bss_start:

.word __bss_start

.globl _bss_end

_bss_end:

.word _end

@ Interrupt stack settings, used in cpu_init

#if defined(CONFIG_USE_IRQ)

/* IRQ stack memory (calculated at run-time) */

.globl IRQ_STACK_START

IRQ_STACK_START:

.word 0x0badc0de

/* IRQ stack memory (calculated at run-time) */

.globl FIQ_STACK_START

FIQ_STACK_START:

.word 0x0badc0de

#endif /* CONFIG_USE_IRQ */

/*

 * the actual reset code

 */

 @ ARM reset execution is the program here. The above exception will only be executed when an exception occurs.

reset:

/*

* set the cpu to SVC32 mode and IRQ & FIQ disable

*/

@;mrs r0,cpsr

@;bic r0,r0,#0x1f

@;orr r0,r0,#0xd3

@;msr cpsr,r0

@ Set the CPU to svc32 mode and disable interrupts; msr writes 0xd3 to cpsr_c

31 30 29 28 --- 7 6 - 4 3 2 1 0 Description

        N Z C V I F M4 M3 M2 M1 M0  

                                   0 0 0 0 0 User mode

                                   0 0 0 0 1 FIQ mode

                                   0 0 0 1 0 IRQ mode

                                   0 0 0 1 1 SVC mode

                                   1 0 0 0 0 User mode

                                   1 0 0 0 1 FIQ mode

                                   1 0 0 1 0 IRQ mode

                                   1 0 0 1 1 SVC mode

                                   1 0 1 1 1 ABT mode

                                   1 1 0 1 1 UND mode

msr cpsr_c, #0xd3 @ I & F disable, Mode: 0x13 - SVC   1101 0011

/*

 *************************************************************************

 *

 * CPU_init_critical registers

 *

 * setup important registers

 * setup memory timing

 *

 *************************************************************************

 */

         /*

         * we do sys-critical inits only at reboot,

         * not when booting from ram!

         */

@ cpu initialization

cpu_init_crit:

@CONFIG_EVT1 is defined, this section is not executed

#ifndef CONFIG_EVT1

#if 0

bl v7_flush_dcache_all

#else

bl disable_l2cache  

mov r0, #0x0 @ 

mov r1, #0x0 @ i

mov r3, #0x0

mov r4, #0x0

lp1:

mov r2, #0x0 @ j

lp2:

mov r3, r1, LSL #29 @ r3 = r1(i) <<29

mov r4, r2, LSL #6 @ r4 = r2(j) <<6

orr r4, r4, #0x2 @ r3 = (i<<29)|(j<<6)|(1<<1)

orr r3, r3, r4

mov r0, r3 @ r0 = r3

bl CoInvalidateDCacheIndex

add r2, #0x1 @ r2(j)++

cmp r2, #1024 @ r2 < 1024

bne lp2 @ jump to lp2

add r1, #0x1 @ r1(i)++

cmp r1, #8 @ r1(i) < 8

bne lp1 @ jump to lp1

bl set_l2cache_auxctrl

bl enable_l2cache

#endif

#endif

bl disable_l2cache @ Disable I/D-cache

bl set_l2cache_auxctrl_cycle

bl enable_l2cache @ Enable I/D-cache

       /*

        * Invalidate L1 I/D

        */

@ ARM Architecture Reference Manual.pdf has an example on page 745, you can search for CP15

@ CP15 — the system control coprocessor

@ Provide specific registers to configure and control caches, MMU, protection system, and configure clock mode (used in bootloader clock initialization) through coprocessor instructions MCR and MRC

        @ Register 7 - Cache control   Register 8 - TLB operations

mov r0, #0                  @ set up for MCR

        mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs Close the cache of the TLB buffer page table (the table that converts virtual machine addresses to physical addresses)

        mcr p15, 0, r0, c7, c5, 0 @ invalidate icache icache buffers instruction I-cache

       /*

        * disable MMU stuff and caches

        */

@ Turn off MMU and cache --- Analyze register 1 of cp15

        mrc p15, 0, r0, c1, c0, 0  

        bic r0, r0, #0x00002000     @ clear bits 13 (--V-)

        bic r0, r0, #0x00000007     @ clear bits 2:0 (-CAM)

        orr r0, r0, #0x00000002     @ set bit 1 (--A-) Align

        orr r0, r0, #0x00000800     @ set bit 12 (Z---) BTB

        mcr p15, 0, r0, c1, c0, 0  

        /* Read booting information */

        ldr r0, =PRO_ID_BASE

        ldr r1, [r0,#OMR_OFFSET]

        bic r2, r1, #0xffffffc1

/*Power management, keep power supply*/

#ifdef CONFIG_TQ210_IIC_PM_CHIP

/* PS_HOLD(GPJ2_5) set to output high */

ldr r0, =ELFIN_GPIO_BASE

ldr r1, =0x00100000

str r1, [r0, #GPJ2CON_OFFSET]

ldr r1, =0x0400

str r1, [r0, #GPJ2PUD_OFFSET]

ldr r1, =0x20

str r1, [r0, #GPJ2DAT_OFFSET]

#endif /* CONFIG_TQ210_IIC_PM_CHIP */

#ifdef CONFIG_VOGUES

/* PS_HOLD(GPH0_0) set to output high */

ldr r0, =ELFIN_GPIO_BASE

ldr r1, =0x00000001

str r1, [r0, #GPH0CON_OFFSET]

ldr r1, =0x5500

str r1, [r0, #GPH0PUD_OFFSET]

ldr r1, =0x01

str r1, [r0, #GPH0DAT_OFFSET]

#endif

    @ Boot mode nand, SD, nor

/* NAND BOOT */

cmp r2, #0x0 @ 512B 4-cycle

moveq r3, #BOOT_NAND

cmp r2, #0x2 @ 2KB 5-cycle

moveq r3, #BOOT_NAND

cmp r2, #0x4 @ 4KB 5-cycle 8-bit ECC