MLA : Multiplication with Accumulation
(Multiplication with Accumulate)
MLA{condition}{S} , , , dest = (op_1 * op_2) + op_3
MLA behaves the same as MUL, but it adds the value of operand 3 to the result. This is useful for finding sums.
MUL : Multiplication
(Multiplication)
MUL{condition}{S} , , dest = op_1 * op_2
MUL provides 32-bit integer multiplication. If the operands are signed, the result is assumed to be signed.
Comparison Instructions
Instruction format:
Annotation: CMP and CMP are arithmetic instructions, TEQ and TST are logical instructions. The reason for grouping them together is that their S bits are always set, that is, they always affect the flag bit.
CMN : compare negative values
(Compare Negative)
CMN{condition}{P} , status = op_1 - (- op_2)
CMN is the same as CMP, but it allows you to compare with small negative values (the negation of operand 2), such as -1 to terminate a list, which is difficult to implement otherwise. Thus a comparison with -1 would use:
CMN R0, #1 ; compare R0 with -1
See CMP instruction for details.
CMP : Comparison
(Compare)
CMP{condition}{P} , status = op_1 - op_2
CMP allows the contents of a register to be compared to the contents of another register or an immediate value, changing the status flags to allow conditional execution. It does a subtraction, but does not store the result, but rather changes the flags appropriately. The flags indicate how operand 1 compares to operand 2 (size, etc.). If operand 1 is greater than operand 2, then the instruction following it with the GT suffix will be executed.
Apparently, you don't need to explicitly specify the S suffix to change the status flags... if you do it is ignored.
TEQ : Test Equivalence
(Test Equivalence)
TEQ{Condition}{P} , Status = op_1 EOR op_2
TEQ is similar to TST. The difference is that the conceptual calculation here is EOR instead of AND. This provides a way to see if two operands are equal without affecting the carry flag (unlike CMP). TEQ with a P suffix can also be used to change the flag in R15 (in 26-bit mode).
TST : Test bit
(Test bits)
TST{Condition}{P} , Status = op_1 AND op_2
TST is similar to CMP, except that it does not produce a result placed in the destination register. Instead, it operates on the two operands given and reflects the result on the status flags. Use TST to check whether a specific bit is set. Operand 1 is the data word to be tested and operand 2 is a bit mask. After testing, the Zero flag is set if there is a match, otherwise it is cleared. Like CMP, you do not need to specify the S suffix.
TST R0, #%1 ; Test whether bit 0 is set in R0.
Branch Instructions
B : Branch
(Branch)
B{condition}
B is the simplest branch. Once a B instruction is encountered, the ARM processor will immediately jump to the given address and continue execution from there. Note that the actual value stored in the branch instruction is an offset relative to the current value of R15; it is not an absolute address. Its value is calculated by the assembler. It is a 24-bit signed number, which is extended to 32 bits after being shifted left by two bits, indicating an effective offset of 26 bits (+/- 32M).
On other processors, you may often see instructions like this:
OPT 1 LDA &70 CMP #0 BEQ Zero STA &72 .Zero RTS On an ARM processor, these will become something like this:
OPT 1 ADR R1, #&70 LDR R0, [R1] CMP #0 BEQ Zero STR R0, [R1, #2] .Zero MOV PC, R14
This is not a great example, but you can imagine how it would be better to use conditional execution instead of branching. On the other hand, if you have large sections of code or your code uses status flags, you can use conditional execution to implement various branches: so that a single simple conditional execution instruction can replace all these branches and jumps that exist in other processors.
OPT 1 ADR R1, #&70 LDR R0, [R1] CMP R0, #0 STRNE R0, [R1, #2] MOV PC, R14
BL : Branch with connection
(Branch with Link)
BL{condition}
BL is another branch instruction. Just before the branch, register 14 is loaded with the contents of R15. You can return to the instruction after the branch by reloading R14 into R15.
It is a basic but powerful implementation of a subroutine. Its use is best demonstrated in Screen Loader 2 (Example 4)...
.load_new_format BL switch_screen_mode BL get_screen_info BL load_palette .new_loop MOV R1, R5 BL read_byte CMP R0, #255 BLEQ read_loop STRB R0, [R2, #1]!
Here we see three subroutines called before the loader loop. Then, within the loop, the read_byte subroutine is called once the conditional execution is met.
Conditional Execution
A very special feature of the ARM processor is its conditional execution. We don't mean the basic if carry then branch, ARM takes this logic stage one step further to if carry then XXX - where XXX is anything.
For example, here is a list of branch instructions for the Intel 8086 processor:
JA Jump if Above JAE Jump if Above or Equal JB Jump if Below JBE Jump if Below or Equal JC Jump if Carry JCXZ Jump if CX Zero (CX is a register that can be used for loop counts) JE Jump if Equal JG Jump if Greater than JGE Jump if Greater than or Equal JL Jump if Less than JLE Jump if Less Than or Equal JMP JuMP JNA Jump if Not Above JNAE Jump if Not Above or Equal JNB Jump if Not Below JNBE Jump if Not Below or Equal JNC Jump if No Carry JNE Jump if Not Equal JNG Jump if Not Greater than JNGE Jump if Not Greater than or Equal JNL Jump if Not Less than JNLE Jump if Not Less than or Equal JNO Jump if Not Overflow JNP Jump if Not Parity JNS Jump if Not Sign JNZ Jump if Not Zero JO Jump if Overflow JP Jump if Parity JPE Jump if Parity Even JPO Jump if Parity Odd JS Jump if Sign JZ Jump if Zero 80386 Added: JECXZ Jump if ECX Zero
In contrast, ARM processors only offer:
B Branch BL Branch with connection
But ARM provides conditional execution, which allows you to work around this seemingly inflexible limitation:
BEQ Branch if EQual BNE Branch if Not Equal BVS Branch if oVerflow Set BVC Branch if oVerflow Clear BHI Branch if HIgher BLS Branch if Lower or the Same BPL Branch if PLus B MI Branch if MInus BCS Branch if Carry Set BCC Branch if Carry Clear BGE Branch if Greater than or Equal BGT Branch if Greater Than BLE Branch if Less than or Equal BLT Branch if Less Than BLEQ Branch with Link if EQual .... BLLT Branch with Link if Less Than
There are two more codes,
AL - ALways, default condition so no need to specify
NV - Never, not very useful. You should not use this code anyway...
The critical moment comes when you discover that all Bxx instructions are actually the same instruction.
Then you might wonder, if you can add all these conditions to a branch instruction, can you add them to a register load instruction? The answer is yes.
The following is a list of the available condition codes:
EQ : Equal
If the Z flag is set after a comparison.
NE : Not equal to
If the Z flag is cleared after a comparison.
VS : Overflow Setting
If the V flag is set after an arithmetic operation, the result of the calculation will not fit into a 32-bit destination register.
VC : Overflow Clear
If the V flag is cleared, the opposite of VS.
HI : Higher than (unsigned)
If after a comparison the C flag is set and the Z flag is cleared.
LS : Less Than or Same As (unsigned)
If the C flag is cleared or the Z flag is set after a comparison operation.
PL : Positive sign
If an arithmetic operation clears N. For the purposes of defining 'positive sign', zero is positive because it is not negative...
MI : Negative sign
If the N flag is set after an arithmetic operation.
CS : Carry Set
If the C flag is set after an arithmetic operation or a shift operation, and the result of the operation cannot be represented as 32 bits, you can treat the C flag as the 33rd bit of the result.
CC : Carry Clear
The opposite of CS.
GE : Greater than or equal to (signed)
If after a comparison... the N flag is set and the V flag is set or... the N flag is cleared and the V flag is cleared.
GT : Greater than (signed)
If after a comparison... the N flag is set and the V flag is set or... the N flag is cleared and the V flag is cleared and... the Z flag is cleared.
LE : Less than or equal (signed)
If after a comparison... the N flag is set and the V flag is cleared or... the N flag is cleared and the V flag is set and... the Z flag is set.
LT : Less than (signed)
If after a comparison... the N flag is set and the V flag is cleared. Or... the N flag is cleared and the V flag is set.
AL : Always
The default condition, so no need to declare it explicitly.
NV : Never
Not particularly useful, it means that this instruction should never be executed. A poor man's NOP.
NV is included for completeness (as opposed to AL), and you should not use it in your code.
There is a condition code S at the end which works the other way around. When used with an instruction, it causes the status flags to be changed. This does not happen automatically - unless the purpose of the instruction is to set the status. For example:
ADD R0, R0, R1 ADDS R0, R0, R1 ADDEQS R0, R0, R1
The first example is a basic addition (add the value of R1 to R0) which does not affect the status register.
The second example is the same addition, except that it results in a change to the status register.
The last example is the same addition, changing the status register. The difference is that it is a conditional instruction. It is executed only if the result of the previous operation was EQ (if the Z flag is set).
Here is an example of conditional execution at work. You compare register 0 with the contents stored in register 10.
If it is not equal to R10, then call a software interrupt, increment it and branch back to do it again. Otherwise clear R10 and return to the part of the code that called it (whose address is stored in R14).
An example of conditional execution .loop ; mark the start of the loop CMP R0, R10 ; compare R0 with R10 SWINE &40017 ; not equal: call SWI &40017 ADDNE R0, R0, #1 ; add 1 to R0 BNE loop ; branch to 'loop' MOV R10, #0 ; equal: set R10 to zero LDMFD R13!, {R0-R12,PC} ; return to caller
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Recommended ReadingLatest update time:2024-11-17 10:32
Professor at Beihang University, dedicated to promoting microcontrollers and embedded systems for over 20 years.
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